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MSP430FR5994 Datasheet(PDF) 42 Page - Texas Instruments |
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MSP430FR5994 Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 166 page  42 MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962 SLASE54 – MARCH 2016 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962 Specifications Copyright © 2016, Texas Instruments Incorporated 5.11.5 Digital I/Os The digital I/O features include: • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Programmable pullup or pulldown on all ports. • Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of ports P1, P2, P3, P4, P5, P6, P7, and P8. • Read and write access to port control registers is supported by all instructions. • Ports can be accessed byte-wise or word-wise in pairs. • All pins of ports P1, P2, P3, P4, P5, P6, P7, P8, and PJ support capacitive touch functionality. • No cross-currents during start-up. Table 5-11 lists the characteristics of the digital inputs. (1) If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-M Ω resistor in series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN or PJ.5/LFXOUT. (2) The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. (3) The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. (4) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). (5) Not applicable if RST/NMI pin configured as NMI . Table 5-11. Digital Inputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VIT+ Positive-going input threshold voltage 2.2 V 1.2 1.65 V 3.0 V 1.65 2.25 VIT– Negative-going input threshold voltage 2.2 V 0.55 1.00 V 3.0 V 0.75 1.35 Vhys Input voltage hysteresis (VIT+ – VIT–) 2.2 V 0.44 0.98 V 3.0 V 0.60 1.30 RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = VCC 20 35 50 k Ω CI,dig Input capacitance, digital only port pins VIN = VSS or VCC 3 pF CI,ana Input capacitance, port pins with shared analog functions(1) VIN = VSS or VCC 5 pF Ilkg(Px.y) High-impedance input leakage current See (2) and (3) 2.2 V, 3.0 V –20 +20 nA t(int) External interrupt timing (external trigger pulse duration to set interrupt flag)(4) Ports with interrupt capability (see block diagram and terminal function descriptions). 2.2 V, 3.0 V 20 ns t(RST) External reset pulse duration on RST (5) 2.2 V, 3.0 V 2 µs |
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