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ADC10064CIWM/UGN8 Datasheet(PDF) 6 Page - Texas Instruments

Part No. ADC10064CIWM/UGN8
Description  A/D Converter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC10064CIWM/UGN8 Datasheet(HTML) 6 Page - Texas Instruments

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ADC10061, ADC10062, ADC10064
SNAS069E – JUNE 1999 – REVISED MARCH 2013
www.ti.com
AC Electrical Characteristics (continued)
The following specifications apply for V
+ = +5V, t
r = tf = 20 ns, VREF(+) = 5V, VREF(
−) = GND, and Speed Adjust pin unconnected
unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C.
Units
Symbol
Parameter
Conditions
Typical(1)
Limit(2)
(Limit)
RSA = ∞
850
1400
ns (max)
tCRD
Mode 2 Conversion Time
Mode 2, RSA = 18k
530
ns
Access Time (Delay from Falling Edge of
tACC1
Mode 1; CL = 100 pF
30
60
ns (max)
RD to Output Valid)
Access Time (Delay from Falling Edge of
tACC2
Mode 2; CL = 100 pF
900
tCRD + 50
ns (max)
RD to Output Valid)
tSH
Minimum Sample Time(3)
Figure 4(2)
250
ns (max)
TRI-STATE Control (Delay from Rising
t1H, t0H
RL = 1k, CL = 10 pF
30
60
ns (max)
Edge of RD to High-Z State)
Delay from Rising Edge of RD to Rising
tINTH
CL = 100 pF
25
50
ns (max)
Edge of INT
Delay from End of Conversion to Next
tP
50
ns (max)
Conversion
tMS
Multiplexer Control Setup Time
10
75
ns (max)
tMH
Multiplexer Hold Time
10
40
ns (max)
CVIN
Analog Input Capacitance
35
pF (max)
COUT
Logic Output Capacitance
5
pF (max)
CIN
Logic Input Capacitance
5
pF (max)
(3)
Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs. tSH.
TRI-STATE Test Circuits and Waveforms
6
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC10061 ADC10062 ADC10064


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