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TDA3608Q Datasheet(PDF) 6 Page - NXP Semiconductors

Part # TDA3608Q
Description  Multiple voltage regulators with switch
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA3608Q Datasheet(HTML) 6 Page - NXP Semiconductors

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2003 Nov 28
6
Philips Semiconductors
Product specification
Multiple voltage regulators with switch
TDA3608Q; TDA3608TH
FUNCTIONAL DESCRIPTION
The TDA3608 is a multiple output voltage regulator with a
power switch, intended for use in car radios with or without
a microcontroller. Because of low-voltage operation of the
car radio, low-voltage drop regulators are used in the
TDA3608.
Backup supply
The charge of the backup capacitor connected to pin BU
can be used to supply regulator 2 for a short period when
the supply voltage VP drops to 0 V (the time depends on
the value of the capacitor).
Regulator 1
When the output voltage of regulator 2 and the supply
voltage (VP > 4.5 V) are both available, regulator 1 can be
operated by means of enable pin EN1 (see Fig.4).
Regulator 2
Regulator 2 switches on (see Fig.5) when the backup
voltage exceeds 6.5 V for the first time and switches off
when the output voltage of regulator 2 drops below 1.9 V
(this is far below an engine start).
Regulator 3
When the output voltage of regulator 2 and the supply
voltage (VP > 4.5 V) are both available, regulator 3 can be
operated by means of enable pin EN3 (see Fig.4).
Reset
When regulator 2 is switched on and the output voltage of
this regulator is within its voltage range, the reset output
(see Fig.5) will be enabled (pin RES goes HIGH through
an external pull-up resistor) to generate a reset to the
microcontroller.
The reset cycles can be extended by means of an external
capacitor connected to pin CRES. This start-up feature is
included to secure a smooth start-up of the microcontroller
at first connection, without uncontrolled switching of
regulator 2 during the start-up sequence.
Hold
Regulator 1 has an open-collector hold output (see Fig.4)
indicating that the output voltage is settled at 8.5 V.
Pin HOLD is held HIGH by an external pull-up resistor.
When the supply voltage VP drops or during high load, the
output voltage drops out-of-regulation and pin HOLD goes
LOW.
The hold output is only activated when VREG3 > 1.3 V.
When pin HOLD is connected via a pull-up resistor to the
output of regulator 3 spikes will be minimized to 1.3 V
(maximum value) because the hold output is only disabled
when VREG3 < 1.3 V.
Pin HOLD will be forced LOW when the load dump
protection is activated and also in the standby mode.
Power switch
The power switch can be controlled by means of enable
pin ENSW (see Fig.6).
Protections
All output pins are fully protected.
The regulators are protected against load dump
(regulator 1 and regulator 3 switch off at VP > 18 V) and
short-circuit (foldback current protection).
The power switch contains a foldback current protection,
but this protection is delayed at a short-circuit condition by
the reset delay capacitor. During this time the output
current is limited to at least 2 A (peak value) and
1.8 A (continuous value) at VP ≤ 18 V. During the foldback
mode the current is limited to 0.5 A (typical value).
The timing diagram is shown in Fig.7.
The foldback protection is activated when VSW <4V.
When regulator 2 is out-of-regulation and generates a
reset, the power switch is in the foldback mode
immediately when VSW <4V.
In the standby mode the voltage on the reset delay
capacitor is about 4 V and the voltage on the power switch
output is VP − 0.45 V (typical value) at ISW = 1 A. During
an overload condition or short-circuit the reset delay
capacitor will be charged to a higher voltage. The power
switch is in the high current mode while the capacitor is
charged, after this the switch is in the foldback mode
(VSW < 4 V). While the reset delay capacitor is charged the
power switch output can reach its correct output voltage.
Now the voltage on the reset delay capacitor is decreased
rapidly to 4 V. The reset output voltage is not influenced by
this change of voltages. The time of the high current mode
depends on the value of the reset delay capacitor.
At VP > 18 V the power switch is clamped at maximum
17.2 V (to avoid that external connected circuitry is being
damaged by an overvoltage) and the power switch will
switch off at load dump.


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