Write Erase-Verify Command

Setup

Last

Address?

Start

Increment

Address

Read

and Verify

Byte

X = X + 1

Wait = 10 ms

Pass

Write Read Command

X = 1000?

All Bytes =

Interactive

Mode

Write-Erase Command

Program All

Bytes to 00h

Apply VPPL

Power

Down

Apply VPPL

Address = 00h

VCC = 5 V ± 10%, VPP = 12 V ± 5%

X = 1

Device Passed

Device Failed

No

Yes

No

Yes

Fail

No

Yes

Wait = 6

µs

Preprogram

00h ?

Write Set-Up-Erase Command

TMS28F020

262144 BY 8 BIT

FLASH MEMORY

SMJS020C − OCTOBER 1994 − REVISED JANUARY 1998

9

POST OFFICE BOX 1443

Bus

Operation

Command

Comments

Entire memory must = 00h

before erasure

Use Fastwrite

programming algorithm

Initialize addresses

Standby

Wait for VPP to ramp to

VPPH (see Note A)

Initialize pulse count

Write

Set-Up-Er

ase

Data = 20h

Write

Erase

Data = 20h

Standby

Wait = 10 ms

Write

Erase

Verify

Addr = Byte to verify;

Data = A0h; ends the erase

operation

Standby

Wait = 6

µs

Read

Read byte to verify erasure;

compare output to FFh

Write

Read

Data = 00h; resets register

for read operations

Standby

Wait for VPP to ramp to

VPPL (see Note B)

NOTES: A. Refer to the recommended operating conditions for the value of VPPH .

B. Refer to the recommended operating conditions for the value of VPPL .

Figure 1. Flash-Erase Flowchart: Fasterase Algorithm