TMS27C210A 65536 BY 16BIT UV ERASABLE

TMS27PC210A 65536 BY 16BIT

PROGRAMMABLE READONLY MEMORIES

SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

11

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PROGRAMMING INFORMATION

ten(G)†

A0 − A15

DQ0 − DQ15

VPP

VCC

Address Stable

VIH

VIL

VPP‡

VCC

VCC‡

VCC

Program

Verify

tsu(A)

th(A)

tsu(D)

tsu(VPP)

tsu(VCC)

tsu(E)

th(D)

tsu(G)

tw(PGM)

tdis(G)†

Data-In Stable

Data-Out

Valid

Address

N + 1

E

PGM

G

VIH

VIL

VIH

VIL

VIH

VIL

† tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.

‡ 13-V VPP and 6.5-V VCC for SNAP! Pulse programming.

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)