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IDT72V223L10PF Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT72V223L10PF
Description  3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V223L10PF Datasheet(HTML) 9 Page - Integrated Device Technology

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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0
°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns.
6. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7.5ns speed grades.
Commercial
Commercial
Com’l & Ind’l(2)
Commercial
BGA & TQFP
BGA & TQFP
TQFP Only
TQFP Only
IDT72V223L6
IDT72V223L7-5
IDT72V233L6
IDT72V233L7-5
IDT72V243L6
IDT72V243L7-5
IDT72V253L6
IDT72V253L7-5
IDT72V263L6
IDT72V263L7-5
IDT72V263L10
IDT72V263L15
IDT72V273L6
IDT72V273L7-5
IDT72V273L10
IDT72V273L15
IDT72V283L6
IDT72V283L7-5
IDT72V283L10
IDT72V283L15
IDT72V293L6
IDT72V293L7-5
IDT72V293L10
IDT72V293L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
166
133.3
100
66.7
MHz
tA
Data Access Time(5)
14
1(5)
51(5)
6.5
1(5)
10
ns
tCLK
Clock Cycle Time
6
7.5
10
15
ns
tCLKH
Clock High Time
2.7
3.5
4.5
6
ns
tCLKL
Clock Low Time
2.7
3.5
4.5
6
ns
tDS
DataSetupTime
2
2.5
3.5
4
ns
tDH
Data Hold Time
0.5
0.5
0.5
1
ns
tENS
Enable Setup Time
2
2.5
3.5
4
ns
tENH
Enable Hold Time
0.5
0.5
0.5
1
ns
tLDS
LoadSetupTime
3
3.5
3.5
4
ns
tLDH
Load Hold Time
0.5
0.5
0.5
1
ns
tRS
Reset Pulse Width(3)
10
10
10
15
ns
tRSS
ResetSetupTime
15
15
15
15
ns
tRSR
Reset Recovery Time
10
10
10
15
ns
tRSF
Reset to Flag and Output Time
15
15
15
15
ns
tRTS
RetransmitSetupTime
3
3.5
3.5
4
ns
tOLZ
Output Enable to Output in Low Z(4)
0—
0—
0
0—
ns
tOE
Output Enable to Output Valid(5)
14
1(5)
61(5)
61(5)
8ns
tOHZ
Output Enable to Output in High Z(4,5)
14
1(5)
61(5)
61(5)
8ns
tWFF
Write Clock to
FF or IR
—4
—5
6.5
10
ns
tREF
Read Clock to
EF or OR
—4
—5
6.5
10
ns
tPAFA
Clock to Asynchronous Programmable Almost-Full Flag
10
12.5
16
20
ns
tPAFS
Write Clock to Synchronous Programmable Almost-Full Flag
4
5
6.5
10
ns
tPAEA
Clock to Asynchronous Programmable Almost-Empty Flag
10
12.5
16
20
ns
tPAES
Read Clock to Synchronous Programmable Almost-Empty Flag
4
5
6.5
10
ns
tHF
Clock to
HF
10
12.5
16
20
ns
tSKEW1
Skew time between RCLK and WCLK for
EF/OR and FF/IR
4—
5—
7
9—
ns
tSKEW2
Skew time between RCLK and WCLK for
PAE and PAF
5—
7—
10
14
ns


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