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TMDS3200051 Datasheet(PDF) 9 Page - Texas Instruments |
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TMDS3200051 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 44 page  TMS320C511A DIGITAL SIGNAL PROCESSOR SPRS053 – FEBRUARY 1997 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 16 × 16-bit parallel multiplier The ’C511A uses a 16 × 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation in the multiplier. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated with the multiplier: TREG0, a 16-bit temporary register that holds one of the operands for the multiplier, and PREG, the 32-bit product register that holds the product. Four product-shift modes (PM) are available at the PREG’s output. These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM. The multiply instruction (MPY) allows the product to be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers. A 4-bit shift is used in conjunction with the MPY instruction with a short-immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can, instead, be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. The load-TREG0 (LT) instruction normally loads TREG0 to provide one operand (from the data bus), and the MPY instruction provides the second operand (also from the data bus). A multiplication also can be performed with a short- or long-immediate operand by using the MPY instruction with an immediate operand. A product is obtained every two cycles except when a long-immediate operand is used. Four multiply/accumulate instructions (MAC, MACD, MADD, and MADS as defined in Table 4) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations is transferred to the multiplier during each cycle through the program and data buses. This facilitates single-cycle multiply/accumulates when used with repeat ( RPT and RPTZ ) instructions. In these instructions, the coefficient addresses are generated by the PC, while the data addresses are generated by the auxiliary register arithmetic unit. This allows the repeated instruction to access the values sequentially from the coefficient table and step through the data in any of the indirect addressing modes. The RPTZ instruction also clears the accumulator and the product register to initialize the multiply/accumulate operation. The MACD and MADD instructions, when repeated, support filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to eliminate the oldest sample. Circular addressing with MAC and MADS instructions also can be used to support filter implementation. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The ’C511A provides a register file containing eight auxiliary registers (AR0 – AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary-register pointer (ARP) that is loaded with a value from 0 through 7, designated AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the accumulator, the product register, or by an immediate operand defined in the instruction. The contents of these registers can be stored in data memory or used as inputs to the central arithmetic logic unit (CALU). These registers are accessible as memory-mapped locations within the ’C5x data-memory space. The auxiliary register file (AR0 – AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing can be performed either by adding or subtracting 1 or by the contents of the INDX register. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel. |
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