TMS320C511A

DIGITAL SIGNAL PROCESSOR

SPRS053 – FEBRUARY 1997

8

POST OFFICE BOX 1443

32-bit ALU/accumulator

The 32-bit arithmetic logic unit (ALU) and accumulator (ACC) implement a wide range of arithmetic and logical

functions, the majority of which execute in a single clock cycle. The ALU is a general-purpose arithmetic/logic

unit that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition

to the usual arithmetic instructions, the ALU can perform Boolean operations, facilitating the bit manipulation

ability required of a high-speed controller. One input to the ALU is always supplied by the ACC, and the other

input can be furnished from the product register (PREG) of the multiplier, the accumulator buffer (ACCB), or the

output of the scaling shifter (which has been read from data memory or from the ACC). After the ALU performs

the arithmetic or logical operation, the result is stored in the ACC where additional operations, such as shifting,

can be performed. Data input to the ALU can be scaled by the scaling shifter. The 32-bit ACC is split into two

16-bit segments for storage in data memory. Shifters at the output of the ACC provide a left shift of 0 to 7 places.

This shift is performed while the data is being transferred to the data bus for storage. The contents of the ACC

remain unchanged. When the postscaling shifter is used on the high word of the ACC (bits 31 – 16), the most

significant bits (MSBs) are lost and the least significant bits (LSBs) are filled with bits shifted in from the low word

(bits 15 – 0). When the postscaling shifter is used on the low word, the LSBs are filled with zeros.

The ’C511A supports floating-point operations for applications requiring a large dynamic range. By performing

left shifts, the normalization instruction (NORM) is used to normalize fixed-point numbers contained in the ACC.

The four bits of TREG1 (the temporary register for dynamic shift count) define a variable shift through the scaling

shifter for the ADDT/LACT/SUBT instructions (add to / load to / subtract from ACC with shift specified by TREG1).

These instructions are useful in denormalizing a number (that is, converting from floating point to fixed point).

They are also useful for executing an automatic gain control (AGC) going into a filter.

The single-cycle 1-bit to 16-bit right shift of the ACC efficiently aligns the ACC’s contents. This, coupled with

the 32-bit temporary buffer on the ACC, enhances the effectiveness of the ALU in extended-precision arithmetic.

The ACCB provides a temporary storage place for a fast save of the ACC. The ACCB also can be used as an

input to the ALU. The minimum or maximum value in a string of numbers is found by comparing the contents

of the ACCB with the contents of the ACC. The minimum or maximum value is placed in both registers, and,

if the condition is met, the carry bit (C) is set to 1. The minimum and maximum functions are executed by the

CRLT and CRGT instructions, respectively. See Table 4 for a list of ’C511A instructions.

scaling shifters

The ’C511A provides a scaling shifter that has a 16-bit input connected to the data bus and a 32-bit output

connected to the ALU. This scaling shifter produces a left shift of 0 to 16 bits on the input data. The shift count

is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of the output

are filled with zeros; the MSBs may either be filled with zeros or sign-extended, depending upon the value of

the sign-extension mode (SXM) bit of status register ST1.

The ’C511A also contains several other shifters that allow it to perform numerical scaling, bit extraction,

extended-precision arithmetic, and overflow prevention. These shifters are connected to the output of the

product register and the ACC.

parallel logic unit

The parallel logic unit (PLU) is a second logic unit, additional to the main ALU, that executes logic operations

on data without affecting the contents of the ACC. The PLU provides the bit-manipulation ability required of a

high-speed controller and simplifies control / status register operations. The PLU provides a direct logic

operation path to data memory space and can set, clear, test, or toggle multiple bits directly in a data memory

location, a control / status register, or any register that is mapped into data memory space.