TMS320C511A

DIGITAL SIGNAL PROCESSOR

SPRS053 – FEBRUARY 1997

1

POST OFFICE BOX 1443

Instruction Execution Time With 5-V

Operation

Program ROM

Program/Data RAM

Code / Decode (CODEC) Interface

Generation Capability

Program Space

Clocking Options

Management

100-Pin Thin Quad Flat Package (PZ Suffix)

Modes:

– 47 mA (2.35 mA/MIPS) at 5 V, 40-MHz

Clock (Average)

– 3 mA at 5 V, 40-MHz Clock

(Typical IDLE2)

– 5

µA at 5 V, Clocks Off

(Typical STANDBY)

description

The TMS320C511A is a member of the ’C5x generation of the Texas Instruments (TI

™) TMS320 digital signal

processors (DSPs). This device is fabricated with static CMOS integrated circuit technology, and its

architectural design is based on that of an earlier TI DSP, the TMS320C25. The combination of advanced

Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis

of the operational flexibility and speed of the ’C511A device. The ’C511A executes up to 50 MIPS (million

instructions per second).

The ’C5x generation DSPs, like the ’C511A, offer these advantages:

Table 1 lists the characteristics of the ’C511A processor: the capacity of on-chip RAM and ROM, the number

of serial and parallel I/O ports, the execution time of one machine cycle, and the type of package with total pin

count.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

TI is a trademark of Texas Instruments Incorporated.

Copyright

© 1997, Texas Instruments Incorporated