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TMX320C6742ZCE Datasheet(PDF) 3 Page - Texas Instruments |
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TMX320C6742ZCE Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 187 page  TMS320C6742 www.ti.com SPRS587E – JUNE 2009 – REVISED MARCH 2014 1.2 Applications • Currency Inspection • Machine Vision (Low-End) • Biometric Identification 1.3 Description The TMS320C6742 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 64-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: one I2C Bus interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; one multichannel buffered serial port (McBSP) with FIFO buffers; one serial peripheral interface (SPI) with multiple chip selects; two 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general- purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; one UART interface (with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution. Device Information PART NUMBER PACKAGE BODY SIZE TMS320C6742ZCE NFBGA (361) 13,00 mm x 13,00 mm TMS320C6742ZWT NFBGA (361) 16,00 mm x 16,00 mm Copyright © 2009–2014, Texas Instruments Incorporated TMS320C6742 Fixed- and Floating-Point DSP 3 Submit Documentation Feedback Product Folder Links: TMS320C6742 |
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