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IDT82V1671 Datasheet(PDF) 81 Page - Integrated Device Technology |
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IDT82V1671 Datasheet(HTML) 81 Page - Integrated Device Technology |
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81 / 107 page  81 RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET INDUSTRIAL TEMPERATURE RANGE LREG20: RSLIC IO Direction Configuration and IO Status Register, Read/Write (13H/93H) IO_C[3:0] RSLIC IO direction configuration. The IO_C[3:0] bits determine the directions of the IO4 to IO1 pins, respectively. IO_C[3] = 0: The IO4 pin of the specified channel is configured as an input (default); IO_C[3] = 1: The IO4 pin of the specified channel is configured as an output. IO_C[2] = 0: The IO3 pin of the specified channel is configured as an input (default); IO_C[2] = 1: The IO3 pin of the specified channel is configured as an output. IO_C[1] = 0: The IO2 pin of the specified channel is configured as an input (default); IO_C[1] = 1: The IO2 pin of the specified channel is configured as an output. IO_C[0] = 0: The IO1 pin of the specified channel is configured as an input (default); IO_C[0] = 1: The IO1 pin of the specified channel is configured as an output. IO[3:0] IO pin status (when the corresponding IO pin is configured as an input) or IO control data (when the corresponding IO pin is configured as an output) IO[3] = 0: The IO4 pin of the specified channel is in logic low state (when configured as an input) or it is set to logic low (when configured as an output); IO[3] = 1: The IO4 pin of the specified channel is in logic high state (when configured as an input) or it is set to logic high (when configured as an output); IO[2] = 0: The IO3 pin of the specified channel is in logic low state (when configured as an input) or it is set to logic low (when configured as an output); IO[2] = 1: The IO3 pin of the specified channel is in logic high state (when configured as an input) or it is set to logic high (when configured as an output); IO[1] = 0: The IO2 pin of the specified channel is in logic low state (when configured as an input) or it is set to logic low (when configured as an output); IO[1] = 1: The IO2 pin of the specified channel is in logic high state (when configured as an input) or it is set to logic high (when configured as an output); IO[0] = 0: The IO1 pin of the specified channel is in logic low state (when configured as an input) or it is set to logic low (when configured as an output); IO[0] = 1: The IO1 pin of the specified channel is in logic high state (when configured as an input) or it is set to logic high (when configured as an output); Once the IOn pin is configured as an input, each change of the corresponding IO[n] bit will generate an interrupt if the mask bit IO_M[n] in LREG19 is set to 0. A read command to this register will clear the interrupt caused by changes of the IO[3:0] bits. LREG21: Interrupt Source Register, Read Only (14H) FEED_I DC feeding characteristic indication bit for the constant current zone. Whenever the DC feeding is operated at the constant zone, the FEED_I is set to 1, otherwise it is set to 0. FEED_V DC feeding characteristic indication bit for the constant voltage zone. Whenever the DC feeding is operated at the constant voltage zone, the FEED_V bit it is set to 1, otherwise it is set to 0. FEED_R DC feeding characteristic indication bit for the resistive zone. Whenever the DC feeding is operated at the resistive zone, the FEED_R bit is set to 1, otherwise it is set to 0. b7 b6 b5 b4 b3 b2 b1 b0 Command R/W 0010 011 I/O data IO_C[3] IO_C[2] IO_C[1] IO_C[0] IO[3] IO[2] IO[1] IO[0] b7 b6 b5 b4 b3 b2 b1 b0 Command 0 0010 100 I/O data FEED_I FEED_V FEED_R LM_OK UTD_OK OTMP RAMP_OK GK_POL |
Similar Part No. - IDT82V1671 |
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Similar Description - IDT82V1671 |
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