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COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT23S09

3.3VZERODELAYCLOCKBUFFER

OCTOBER 2003

2003 Integrated Device Technology, Inc.

DSC - 6395/3

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bank of

four outputs

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• IDT23S09-1 for Standard Drive

• IDT23S09-1H for High Drive

• No external RC network required

• Spread spectrum compatible

• Available in SOIC and TSSOP packages

IDT23S09

3.3V ZERO DELAY

CLOCK BUFFER, SPREAD

SPECTRUM COMPATIBLE

DESCRIPTION:

The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09

accepts one reference input, and drives two banks of four low skew clocks.

The -1H version of this device operates up to 133MHz frequency and has

higher drive than the -1 device. All parts have on-chip PLLs which lock

to an input clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad. In the absence of an input clock, the

IDT23S09 enters power down. In this mode, the device will draw less than

12µAforCommercialTemperaturerangeandlessthan25µAforIndustrial

temperature range, and the outputs are tri-stated.

The IDT23S09 is characterized for both Industrial and Commercial

operation.

PLL

S1

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Control

Logic

1

REF

S2

16

CLKOUT

8

9

2

3

14

15

6

7

10

11

FUNCTIONAL BLOCK DIAGRAM