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TDA8260TW Datasheet(PDF) 8 Page - NXP Semiconductors |
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TDA8260TW Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 23 page 2004 Sep 03 8 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer TDA8260TW PROGRAMMABLE ADDRESSES The programmable address bits MA1 and MA0 offer the possibility of having up to four TDA8260TW devices in the same system. The relationship between the voltage applied to pin AS and the value of bits MA1 and MA0 is given in Table 3. Table 3 I2C-bus address selection PROGRAMMABLE MAIN DIVIDER RATIO Program bytes PD1 and PD2 contain the fifteen bits N14 to N0 that set the main divider ratio. The ratio N = N14 × 214 + N13 × 213 +...+ N1 × 2 + N0. OPERATING AND TEST MODES The mode of operation is set using bits T2, T1 and T0 in control byte CD1; see Table 4. Table 4 Mode selection Note 1. Status at power-on: the tuning voltage output is released and pin VT is in the high-impedance state. REFERENCE DIVIDER Five reference divider ratios allow the adjustment of the comparison frequency to different values depending on the compromise that has to be found between step size and phase noise. The reference divider ratios and the corresponding comparison frequencies are programmed using bits R2, R1 and R0; see Table 5. Table 5 Reference divider ratio CHARGE PUMP CURRENT Four values of charge pump current can be chosen using bits C1 and C0; see Table 6. Table 6 Charge pump current VAS MA1 MA0 0 to 0.1VCC 00 open-circuit 0 1 0.4VCC to 0.6VCC 10 0.9VCC to VCC 11 T2 T1 T0 MODE XTOUT 0 0 0 normal operation OFF 0 0 1 POR state = CP sink(1) fXTAL 010 1/2 × fDIV 1/2 × fDIV 0 1 1 CP sink fXTAL 1 0 0 normal operation fXTAL 101 2 × fref 2 × fref 1 1 0 CP OFF fXTAL 1 1 1 CP source fXTAL R2 R1 R0 DIVIDER RATIO COMPARISON FREQUENCY 000 2 2 MHz 001 4 1 MHz 0 1 0 8 500 kHz 0 1 1 not allowed 1 0 0 not allowed 1 0 1 16 250 kHz 1 1 0 not allowed 1 1 1 32 125 kHz C1 C0 TYPICAL CHARGE PUMP CURRENT ABSOLUTE VALUES ( µA) 0 0 420 0 1 900 1 0 1360 1 1 2320 |
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