15

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15

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TMS34094

ISA BUS INTERFACE

SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992

POST OFFICE BOX 1443

9

BKPORT

Bank Select Data Port

This register is used to access the bank select address (BKADn) or bank select mask (BKMSKn) register

indexed by BPNT3–BPNT0 in the BSCTL register. BPNT3–BPNT0 are autoincremented after every 16-bit

access to BKPORT. This register is uninitialized after reset.

BKAD0L–BKAD3L

BKAD0H–BKAD3H

Bank Addressx Low

Bank Addressx High

These registers are used to specify the four address compare values for the bank decode logic. Each set of

16-bit BKADxL and 16-bit BKADxH values is treated as a 32-bit BKADx value. Each 32-bit BKADx value is

masked using the corresponding BKMSKx value, compared with the LAD bus address bits allowed by the

corresponding BKMSKx value and conditioned based on LAD bus cycle type, to generate the corresponding

BSELx output. BKCTL provides selective control over whether a BSELx output will or will not respond to DRAM

refresh or VRAM special cycles (see

BKCTL, page 10).

Each 32-bit BKADx register is accessed via the BKPORT register as two 16-bit halves, BKADxL and BKADxH.

The BPNT3–BPNT0 bits of the BKCTL register select which bank select register is accessed during a read or

write of BKPORT.

Host write accesses to BKAD0–BKAD3 may cause improper decode of ongoing TMS34020 local bus cycles.

Do not write to any BKAD0–BKAD3 register when the TMS34020 is performing any operation which could be

adversely affected by improper address decoding, including execution of code.

BKMSK0L–BKMSK3L

BKMSK0H–BKMSK3H

Bank MASKx Low

Bank MASKx High

These registers are used to specify the four mask values for the bank decode logic. Each set of 16-bit BKMSKxL

and 16-bit BKMSKxH values are treated as a 32-bit BKMSKx value. Each 32-bit BKMSKx value is used to mask

the corresponding BKADx value and the LAD31–LAD0 values which are then compared to determine which

BSELx output to activate for the given LAD bus cycle. BKCTL provides selective control over whether a BSELx

output will or will not respond to DRAM refresh or VRAM special cycles (see

BKCTL, page 10).

A BKMSKx bit set to 1 allows comparison of the corresponding BKADx bit with the corresponding LAD bus

address bit. A BKMSKx bit set to zero causes the 34094 to disregard the corresponding BKADx and LAD bus

address bit in the comparison.