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TMS34094 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS34094 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 38 page TMS34094 ISA BUS INTERFACE SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2 local memory decode TMS34020 local memory map decoding is provided by the TMS34094. The TMS34094 internally decodes LAD bus addresses to generate four bank select output signals. The bank select signals may be used to control DRAM, VRAM, ROM and other devices in the TMS34020 local memory map. This programmable decoding allows designs to support multiple resolutions and color depths through software configuration. For applications requiring synchronization of host software and TMS34020 software, the TMS34094 shadows the TMS34020 host control register low (HSTCTLL) as an ISA I/O register. This eliminates a LAD bus host access cycle, thereby reducing LAD bus traffic and increasing TMS34020 performance. To simplify the design of VGA-compatible, single-monitor graphics systems, the TMS34094 supports VGA passthrough. Onchip passthrough logic supports designs where VGA controllers are onboard, as well as designs where a VGA-compatible auxiliary video connector is provided. The TMS34094 decodes ISA Bus accesses to standard VGA palette control registers and signals that a VGA pass-through access is occurring. Shadowing of VGA passthrough cycles may be disabled, enabled for writes only, or enabled for reads and writes. |
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