TM4EN64KPU, TM4EN64NPU 4194304 BY 64BIT

TM8EN64KPU, TM8EN64NPU 8388608 BY 64BIT

EXTENDEDDATAOUT DYNAMIC RAM MODULES

SMMS692 − AUGUST 1997

10

POST OFFICE BOX 1443

capacitance

over recommended ranges of supply voltage and ambient temperature,

f = 1 MHz (see Note 2)

PARAMETER

’4EN64xPU

’8EN64xPU

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

Ci(A)

Input capacitance, A0 − A12

22

42

pF

Ci(OE)

Input capacitance, OEx

30

58

pF

Ci(CAS)

Input capacitance, CASx

9

16

pF

Ci(RAS)

Input capacitance, RASx

30

30

pF

Ci(W)

Input capacitance, WEx

30

58

pF

Co

Output capacitance

9

16

pF

Ci/o(SDA)

Input/output capacitance, SDA input

9

9

pF

Ci(SPD)

Input capacitance,SA0,SA1,SA2,SCL inputs

7

7

pF

NOTE 2: VDD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.

switching characteristics over recommended ranges of supply voltage and ambient temperature

(see Note 3)

PARAMETER

’xEN64xPU-40

’xEN64xPU-50

’xEN64xPU-60

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tAA

Access time from column address (see Note 4)

20

25

30

ns

tCAC

Access time from CASx (see Note 4)

11

13

15

ns

tCPA

Access time from CASx precharge (see Note 4)

22

28

35

ns

tRAC

Access time from RASx (see Note 4)

40

50

60

ns

tOEA

Access time from OEx (see Note 4)

11

13

15

ns

tCLZ

Delay time, CASx to output in low-impedance state

0

0

0

ns

tOEZ

Output buffer turn off delay from OEx (see Note 5)

3

11

3

13

3

15

ns

tREZ

Output buffer turn off delay from RASx (see Note 5)

3

11

3

13

3

15

ns

tCEZ

Output buffer turn off delay from CASx (see Note 5)

3

11

3

13

3

15

ns

tWEZ

Output buffer turn off delay from WEx (see Note 5)

3

11

3

13

3

15

ns

NOTES:

3. With ac parameters, it is assumed that tT = 2 ns.

4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.

5. The MAX specifications of tREZ, tCEZ, tWEZ, and tOEZ are specified when the outputs are no longer driven. Data-in should not be

driven until one of the applicable maximum values is satisfied.

EDO timing requirements

’xEN64xPU-40

’xEN64xPU-50

’xEN64xPU-60

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tHPC

Cycle time, EDO page mode, read-write

16

20

25

ns

tPRWC Cycle time, EDO read-write

47

57

68

ns

tCSH

Delay time, RASx active to CASx precharge

32

40

48

ns

tCHO

Hold time, OEx from CASx

5

5

5

ns

tDOH

Hold time, output from CASx

5

5

5

ns

tCAS

Pulse duration, CASx active (see

6

10 000

8

10 000

10

10 000

ns

tWPE

Pulse duration, WEx active (output disable only)

5

5

5

ns

tCP

Pulse duration, CASx precharge

6

8

10

ns

tOCH

Setup time, OEx before CASx

5

5

5

ns

tOEP

Precharge time, OEx

5

5

5

ns