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S3C2800 Datasheet(PDF) 15 Page - Samsung semiconductor |
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S3C2800 Datasheet(HTML) 15 Page - Samsung semiconductor |
15 / 22 page PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER 13 SIGNAL DESCRIPTIONS Table 3. S3C2800 Signal Descriptions Signal I/O Description BUS CONTROLLER OM[1:0] I OM [1:0] is used to determines the bus width of static memory bank0 (boot ROM). The pull-up/down resistor determines the logic level. 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = Not used ADDR[24:0] O ADDR [24:0] (Address Bus) outputs the memory address of the corresponding bank. DATA[31:0] IO DATA [31:0] (Data Bus) inputs data during memory read and outputs data during memory write. The bus width is programmable among 8/16/32-bit. nSCS[3:0] O nSCS[3:0] (Static memory bank Select) are activated when the address of a static memory is within the address region of each bank. The number of access cycles and the bank size can be programmed. nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle. nWBE[3:0] O Write Byte Enable. nBE[3:0] O 16-bit SRAM Byte Enable. nWAIT I Request to prolong a current bus cycle. As long as nWAIT is Low, the current bus cycle can’t be completed. nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle. ENDIAN I It determines whether or not the data type is Little-endian or Big-endian. The pull- up/down resistor determines the logic level during the reset cycle. ENDIAN value is latched only at the rising edge of nRESET: when nRESET is Low, the ENDIAN (GPC3) pin operates in input mode; nRESET becomes High, the ENDIAN pin will automatically switch to output mode. 0 = Little-endian 1 = Big-endian DRAM/SDRAM nDRAS[3:0] O Row Address Strobe. nDCAS[3:0] O Column Address Strobe. nSDRAS O SDRAM Row Address Strobe. nSDCAS O SDRAM Column Address Strobe. nSDCS[3:0] O SDRAM Chip Select. DQM[3:0] O SDRAM Data Mask. SDCLK O SDRAM Clock (SDCLK = HCLK). SDCKE O SDRAM Clock Enable. INTERRUPT CONTROL UNIT EXTINT[7:0] I External Interrupt request. DMA nXDREQ[1:0] I External DMA request. nXDACK[1:0] O External DMA acknowledge. |
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