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DS3886AV Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DS3886AV Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 11 page AC Electrical Characteristics (Note 5) (Continued) T A = 0˚C to +70˚C, VCC = 5V ±10% Symbol Parameter Conditions Min Typ Max Units RECEIVER t PLZ CD to An Disable Time LE = 3.0V 3 5 10 ns t PZL Enable Time Bn = 2.1V, T/R = 0V ( Figure 8 and Figure 9) 2.5 6 8 ns t PHZ Disable Time LE = 3.0V 4 6 8.5 ns t PZH Enable Time Bn = 1.1V, T/R = 0V ( Figure 8 and Figure 9) 2.5 5 8.5 ns t PLZ T/R to An Disable Time LE = 3.0V, Bn = 2.1V 3 7.5 12 ns t PZL Enable Time CD = 0V ( Figure 10 and Figure 11) 5 9.5 15 ns t PHZ Disable Time LE = 3.0V 3 6 9 ns t PZH Enable Time Bn = 1.1V, CD = 0V ( Figure 8 and Figure 9) 36 9 ns t skew LE to An Same Package (Note 7) 0.5 3 ns Bn to An Same Package (Note 7) 0.5 2.5 ns RECEIVER TIMING REQUIREMENTS ( Figure 7) t S Bn to LE Set-up Time CD = T/R = 0V 3ns t H LE to Bn Hold Time CD = T/R = 0V 1ns t pw LE Pulse Width CD = T/R = 0V 5ns PARAMETERS NOT TESTED C output Capacitance at Bn (Note 8) 5 pF t NR Noise Rejection (Note 9) 1 ns Note 6: Input waveforms shall have a rise and fall time of 3 ns. Note 7: tskew is an absolute value defined as differences seen in propagation delay between drivers in the same package with identical load conditions. Note 8: The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide. Note 9: This parameter is tested during device characterization. The measurements revealed that the part will typically reject 1 ns pulse width. Note 10: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5 V/ns, measured between 1.3V and 1.8V (approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5 Ω tied to +2.1 V DC. Pin Description Pin Name Number of Input/ Description Pins Output A0–A8 9 I/O TTL TRI-STATE receiver output and driver input ACLK 1 I Clock input for latch B0–B8 9 I/O BTL receiver input and driver output B0GND–B8GND 9 NA Driver output ground reduces ground bounce due to high current switching of driver outputs. (Note 11) CD 1 I Chip Disable GND 2 NA Ground reference for switching circuits.(Note 10) LE 1 I Latch Enable LI 1 NA Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 12) NC 5 NA No Connect QGND 1 NA Ground reference for receiver input bandgap reference and non-switching circuits. (Note 11) QV CC 1NA V CC supply for bandgap reference and non-switching circuits. (Note 12) RBYP 1 I Register bypass enable T/R 1 I Transmit/Receive — Transmit (An to Bn) Receive (Bn to An) V CC 2NA V CC supply for switching circuits. (Note 12) Note 11: The multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low iductance (i.e., ground plane with power pins and many signal pins con- www.national.com 5 |
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