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DS3886A Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. DS3886A
Description  BTL 9-Bit Latching Data Transceiver
Download  11 Pages
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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DS3886A Datasheet(HTML) 4 Page - National Semiconductor (TI)

 
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DC Electrical Characteristics (Notes 3, 4) (Continued)
T
A = 0˚ to +70˚C, VCC = 5V ±10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENT
I
CCT
I
CCT — Power Supply Current
T/R = All An = 3.4V, CD = 0.5V
for a TTL High Input
ACLK = LE = RBYP = 3.4V
55
62
mA
(V
IN = VCC − 2.1V)
Supply Current: Sum of V
CC,
T/R = 0.5V, All Bn = 2.1V, LE = CD = 0.5V
45
53
mA
QV
CC and LI
ACLK = RBYP = 3.4V
I
LI
Live Insertion Current
T/R = An = CD = ACLK = 0.5V
1.5
2.2
mA
T/R = All An = RBYB = 2.4V,
CD = ACLK = 0.5V
3
4.5
mA
Note 1: “Absolute maximum ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be
operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All input and/or output pins shall not exceed VCC plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and power
down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVCC and VCC. There is a diode
between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. Alternatively, a current limiting resistor can be used when
pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50 mA. Exception, LI and Bn pins do not have power sequenc-
ing requirements with respect to VCC and QVCC. Furthermore, the difference between VCC and QVCC should never be greater than 0.5V at any time including
power-up.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
All typical values are specified under these conditions: VCC = 5V and TA = 25˚C, unless otherwise stated.
Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second.
Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package.
AC Electrical Characteristics (Note 5)
T
A = 0˚C to +70˚C, VCC = 5V ±10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER
t
PHL
An to Bn
Propagation Delay
CD = 0V, T/ R = RBYP = 3V
13
5
ns
t
PLH
Fall-through mode
(
Figure 1 and Figure 2)
1.5
3
5
ns
t
PHL
ACLK to Bn
Propagation Delay
CD = RBYP = 0V, T/R = 3V
1.7
4
6.5
ns
t
PLH
Latch mode
(
Figure 1 and Figure 4)
2
4
6.5
ns
t
PHL
CD to Bn
Enable Time
T/R = 3V, An = 3V
35
9
ns
t
PLH
Disable Time
(
Figure 1 and Figure 3)
2.5
5
6.7
ns
t
PHL
T/R to Bn
Enable Time
CD = 0V (
Figure 10 and Figure 11),
RBYP = 3V
913
18
ns
t
PLH
Disable Time
CD = 0V (
Figure 10 and Figure 11),
RBYP = 3V
25
8
ns
t
r
Transition Time-Rise/Fall
CD = RBYP = 0V, T/R = 3V
(
Figure 1 and Figure 3) (Note 10)
1
2
3.5
ns
t
f
20% to 80%
12
4
SR
Slew Rate is calculated from
CD = RBYP = 0V, T/R = 3V
0.85
0.5
V/ns
1.3V to 1.8V
(
Figure 1 and Figure 2) (Note 10)
t
skew
ACLK to Bn
Same Package
(Note 7)
0.8
3
ns
An to Bn
Same Package
(Note 7)
0.8
3
ns
DRIVER TIMING REQUIREMENTS (
Figure 4)
t
S
An to ACLK
Set-up Time
CD = RBYP = 0V, T/R = 3V
3ns
t
H
ACLK to An
Hold Time
CD = RBYP = 0V, T/R = 3V
1ns
t
pw
ACLK Pulse Width
CD = RBYP = 0V, T/R = 3V
3ns
RECEIVER
t
PHL
Bn to An
Propagation Delay
CD = T/ R = 0V, LE = 3V
3
4.5
6
ns
t
PLH
Bypass Mode
(
Figure 5 and Figure 6)
3
4.5
6.5
ns
t
PHL
LE to An
Propagation Delay
CD = T/ R = 0V
3.5
5.5
10
ns
t
PLH
Latch Mode
(
Figure 5 and Figure 7)
4.5
5.5
8.5
ns
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