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ICPL2611 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. ICPL2611
Description  HIGH CMR, VERY HIGH SPEED OPTICALLY COUPLED ISOLATOR LOGIC GATE OUTPUT
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ICPL2611 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

   
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SWITCHING SPECIFICATIONS AT T
A = 25°C ( VCC = 5V, IF = 7.5mA Unless otherwise noted )
PARAMETER
SYM DEVICE
MIN TYP MAX UNITS TEST CONDITION
Propagation Delay Time
to Logic Low at Output
t
PHL
25
45
75
ns
R
L = 350Ω, CL = 15pF
( fig 1 )( note4 )
Propagation Delay Time
to Logic High at Output
t
PLH
20
45
75
ns
R
L = 350Ω, CL = 15pF
( fig 1 )( note5 )
Propagation Delay Time
of Enable from V
EH to VEL
t
EHL
20
ns
R
L = 350Ω, CL = 15pF
( note6 )
V
EL = 0V, V EH = 3.5V
Propagation Delay Time
of Enable from V
EL to VEH
t
ELH
20
ns
R
L = 350Ω, CL = 15pF
( note7 )
V
EL = 0V, V EH = 3.5V
Common Mode Transient
Immunity at Logic High
CM
H
10000
V/
µs
I
F = 0mA, VCM = 50VPP
Level Output ( fig 2 )( note8 )
R
L= 350Ω,VOH= 2Vmin.
Common Mode Transient
Immunity at Logic Low
CM
L
10000
V/
µs
V
CM= 50VPP
Level Output ( fig 2 )( note9 )
R
L=350Ω,VOL=0.8Vmax.
NOTES:-
1
Bypassing of the power supply line is required, with a 0.01
µF ceramic disc capacitor adjacent to
each isolator. The power supply bus for the isolator(s) should be seperate from the bus for any
active loads. Otherwise a larger value of bypass capacitor (up to 0.1
µF) may be needed to supress
regenerative feedback via the power supply.
2
Peaking circuits may produce transient input currents up to 50mA, 50ns maximum pulse width,
provided average current does not exceed 20mA.
3
Device considered a two terminal device; pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7
and 8 shorted together.
4
The t
PHL propagation delay is measured from the 3.75 mA level Low to High transition of the input
current pulse to the 1.5V level on the High to Low transition of the output voltage pulse.
5
The t
PLH propagation delay is measured from the 3.75mA level High to Low transition of the input
current pulse to the 1.5V level on the Low to High transition of the output voltage pulse.
6
The t
EHL enable input propagation delay is measured from the 1.5V level on the Low to High transition of
the enable input voltage pulse to the 1.5V level on the High to Low of the output voltage pulse.
7
The t
ELH enable input propagation delay is measured from the 1.5V level on the High to Low transition of
the enable input voltage pulse to the 1.5V level on the Low to High of the output voltage pulse.
8
CM
H is the maximum tolerable rate of rise of the common mode voltage to assure that the output
will remain in a high logic state (ie Vout > 2.0V).
9
CM
L is the maximum tolerable rate of fall of the common mode voltage to assure that the output
will remain in a low logic state (ie Vout < 0.8V)
10
No external pull up is required for a high logic state on the enable input.
DB91019-AAS/A2
30/7/03
FIG.1 SWITCHING TEST CIRCUIT
2
I
F Monitor
0
I
F
V
O
1.5V
100
1.5V
5V
t
PHL
t
PLH
V
OL
R
L
V
O
C
L = 15pF
8
7
6
5
PULSE
GENERATOR
Z
O = 50Ω
t
r = 5ns
I
F
1
4
3
10% Duty Cycle
1/f < 100
µs
5V


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