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TLV320AIC3120 Datasheet(PDF) 95 Page - Texas Instruments |
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TLV320AIC3120 Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 160 page  95 TLV320AIC3120 www.ti.com SLAS653B – FEBRUARY 2010 – REVISED AUGUST 2016 Submit Documentation Feedback Product Folder Links: TLV320AIC3120 Detailed Description Copyright © 2010–2016, Texas Instruments Incorporated Table 7-96. Page 0 / Register 65 (0x41): DAC Volume Control BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D0 R/W 0000 0000 0111 1111–0011 0001: Reserved. Do not write these sequences to these bits. 0011 0000: DAC digital gain = 24 dB 0010 1111: DAC digital gain = 23.5 dB 0010 1110: DAC digital gain = 23 dB ... 0011 0100: DAC digital gain = 18 dB 0010 0011: DAC digital gain = 17.5 dB 0010 0010: DAC digital gain = 17 dB ... 0000 0001: DAC digital gain = 0.5 dB 0000 0000: DAC digital gain = 0 dB 1111 1111: DAC digital gain = –0.5 dB ... 1000 0010: DAC digital gain = –63 dB 1000 0001: DAC digital gain = –63.5 dB 1000 0000: Reserved. Do not use. Table 7-97. Page 0 / Register 66 (0x42): Reserved BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D0 R/W 0000 0000 Reserved. write only reset values. (1) Note that these times are generated using the 1 MHz reference clock which is defined in Page 3 / Register 16. Table 7-98. Page 0 / Register 67 (0x43): Headset Detection BIT READ/ WRITE RESET VALUE DESCRIPTION D7 R/W 0 0: Headset detection disabled 1: Headset detection enabled D6–D5 R XX 00: No headset detected 01: Headset without microphone is detected 10: Reserved 11: Headset with microphone is detected D4–D2 R/W 000 Debounce Programming for Glitch Rejection During Headset Detection(1) 000: 16 ms (sampled with 2-ms clock) 001: 32 ms (sampled with 4-ms clock) 010: 64 ms (sampled with 8-ms clock) 011: 128 ms (sampled with 16-ms clock) 100: 256 ms (sampled with 32-ms clock) 101: 512 ms (sampled with 64-ms clock) 110: Reserved 111: Reserved D1–D0 R/W 00 Debounce programming for glitch rejection during headset button-press detection 00: 0 ms 01: 8 ms (sampled with 1-ms clock) 10: 16 ms (sampled with 2-ms clock) 11: 32 ms (sampled with 4-ms clock) Table 7-99. Page 0 / Register 68 (0x44): DRC Control 1 BIT READ/ WRITE RESET VALUE DESCRIPTION D7 R/W 0 Reserved. Write only the reset value to these bits. D6 R/W 0 0: DRC disabled 1: DRC enabled D5 R/W 0 Reserved. Write only reset value |
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