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TLV320AIC27 Datasheet(PDF) 10 Page - Texas Instruments

Part # TLV320AIC27
Description  STEREO AUDIO CODEC
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLV320AIC27 Datasheet(HTML) 10 Page - Texas Instruments

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TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3D stereo enhancement (continued)
There is no provision for pseudo-stereo effects. Mono signals have no enhancement applied if they are in phase
and have the same amplitude.
Signals from the PCM DAC channels do not have stereo enhancement applied. It is assumed that these signals
have already been processed digitally with any required 3D-enhancement effect. Applying the analog
3D-enhancement will corrupt the digital effect. This is equivalent to setting the POP bit in register 20h. As a
result, the readback value of this bit is fixed as 1, and attempts to change it will be ignored. The POP bit is set
to one and cannot be reset.
variable sample rate support
The DACs and ADCs on this device support all the recommended sample rates specified in the Intel Revision
2.1 specification for both audio and modem rates. Default rates are 48 ksps. If alternative rates are selected,
the AC’97 interface continues to run at 48 kw/s (kilowords per second), but data is transferred across the link
in bursts such that the net sample rate selected is achieved. It is up to the AC’97 Revision 2.1-compliant
controller to ensure that data is supplied to the ac link, and received from the ac link at the appropriate rate.
The device supports on-demand sampling. That is, when the DAC signal-processing circuits need another
sample a request is sent to the controller, which must respond with a data sample in the next frame it sends.
For example, if a rate of 24 ksps is selected, on average the device requests a sample from the controller every
other frame, for each of the stereo DACs. Note that if an unsupported rate is written to one of the rate registers,
the rate defaults to the nearest rate supported. The register then responds when interrogated with the supported
rate the device has defaulted to.
ADCs are controlled similarly but with one difference: normally the left and right-channel ADCs sample at the
same rate.
Table 1. Variable Sample Rates Supported
AUDIO
SAMPLE RATE
CONTROL VALUE
D15–D0
MODEM
SAMPLE RATE
CONTROL VALUE
D15–D0
8000
1F40
7200
1C20
11025
2B11
8228.57 (57600/7)
2024
16000
3E80
8400
20D0
22050
5622
9000
2328
44100
AC44
9600
2580
48000
BB80
10285.71 (72000/7)
282D
12000
2EE0
13714.28 (96000/7)
3592
19200
4B00
24000
5DC0


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