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UCC2541PWP Datasheet(PDF) 8 Page - Texas Instruments |
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UCC2541PWP Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 43 page  UCC2541 SLUS621A − AUGUST 2004 − SEPTEMBER 2005 8 www.ti.com PIN ASSIGNMENTS TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION BST 19 I Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass BST to SW with an external capacitor. CEA− 8 I Inverting input of the current error amplifier used for output current regulation. COMP 9 I Output of the voltage and current error amplifiers for compensation. G1 18 O High-side gate driver output that swings between SW and BST. G2 14 O Low-side gate driver output that swings between PGND and VDRV. G2C 3 I Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH. G2S 12 I Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate dead- time. GND 6 − Ground for internal circuitry. GND and PGND should be tied together under the device. See layout guidelines for further details. PGND 15 − Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias. RAMP 5 I Input pin to connect timing capacitor to GND to generate the oscillator PWM ramp. REF(1) 2 I/O 3.3-V reference pin. All analog control circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1 µF of capacitance for REF loads that are 0 mA to −1 mA. Bypass this pin with at least 1 µF of capacitance if it is used as an input (Mode 3) or if it has large or pulsating loads. RSET 1 I Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current propor- tional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 k Ω to 50 kΩ (giv- ing a programmable nominal ISET range of 30 µA to 150 µA, respectively). SS 11 I Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for imme- diate shutdown functionality. SYNCIN 4 I Input pin for timing signal. Tie to logic high (VREF) when not used. SW 17 − G1 driver return connection. SWS 20 I Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the MOSFET package. TR 10 I Tracking input to the voltage error amplifier. Connect to REF when not used. VDD 16 I Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to 36 V. Bypass the pin with at least 1 µF of capacitance. VDRV 13 I Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the in- ternal logic and control circuitry. VEA− 7 I Inverting input of the voltage error amplifier used for output voltage regulation. (1) REF is an input in Mode 3 only. |
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