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AN-8102 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. AN-8102
Description  Recommendations to Avoid Short Pulse Width Issues
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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AN-8102 Datasheet(HTML) 2 Page - Fairchild Semiconductor

   
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AN-8102
APPLICATION NOTE
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.3
• 4/28/15
2
2. Operation Modes and Avoiding Potential Application Issues
This section discusses three operation condition: normal,
missing output, and abnormal.
VCC
LIN
HIN
GND
VB
HO
VS
LO
Bat1
4
6
7
8
3
1
2
5
FAN7190
0.1µF
Bat2
IN
0.8V
2.5V
Tpulse = 80nS
Figure 3. Evaluation Circuit for HVIC Gate Driver IC
Latch-on can result in keeping the status of output HIGH
even if input is LOW. This condition leads to shoot-through
when HO and LO are turned on at the same time. This failure
mode is the worst case and is discussed in the “Abnormal
Output Operating Condition” section.
2.1. Normal Output Operating Condition
As shown in Figure 4, the SET and RESET pulse is
generated from the pulse generator according to input edge
because the power dissipation of R1 and R2 should be large
in case VB is 600 V. That is why short pulse SET and
RESET is used to reduce power consumption and power
dissipation and size of R1 and R2.
VDD
COM
UVLO
HIN
VB
HO
VS
RST
R
S
Q
6
7
8
1
NOISE
CANCELLER
LO
3
4
5
LIN
2
DELAY
200K
200K
UVLO
VSS/COM
LEVEL
SHIFT
Set
Reset
Control
Latch
Normal input pulse
R1
R2
IN
SET
RESET
Normal input pulse
Q
Figure 4. Normal Operating Simulation Result
The set and reset signal is delivered to set and reset latch
(control latch) circuit through the level-shifter circuit
between the low-voltage circuit and high-voltage circuit.
The control latch circuit keeps output status according to the
SET and RESET pulse signal. The control latch circuit turns
the output circuit on and off and output is generated. That
complex circuit creates the propagation delay between input
and output.
2.2. Missing Output Operating Condition
Missing output means HO is not generated even though
input signal is provided to HIN. Although the pulse
generator generates both SET and RESET pulses according
to input signal, the reconstructed signal by control latch
circuit is too short and is filtered by parasitic RC filter in
RRS latch output circuit. The control latch output signal is
not delivered to the next driver circuit, shown in Figure 5.
IN
SET
RESET
Short input pulse
Q
No output!!
VDD
COM
UVLO
HIN
VB
HO
VS
RST
R
S
Q
6
7
8
1
NOISE
CANCELLER
LO
3
4
5
LIN 2
DELAY
200K
200K
UVLO
VSS/COM
LEVEL
SHIFT
Set
Reset
Control
Latch
R1
R2
Figure 5. Missing Output Operating Simulation Result
Missing output range is from 30 ns to 50 ns at 25°C. With
temperature increasing, the missing output range is shifted
up to around 58 ns, as shown in Figure 7. The short pulse
width, where the missing-operation condition occurs, is also
shifted according to temperature, as shown in Figure 7.
The output is LOW when input pulse width between 39 ns
and 58 ns is provided to input pin.
Figure 6. No Output Operating Waveform
50.5
47
51
51
52
50.5
53.5
52.5
54
54.5
44
46
48
50
52
54
56
1
2
3
4
5
25degC
125degC
Number of Sample
Figure 7. No Output Range According by Temperature


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