Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

AN-8102 Datasheet(PDF) 4 Page - Fairchild Semiconductor

Part No. AN-8102
Description  Recommendations to Avoid Short Pulse Width Issues
Download  5 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo 

AN-8102 Datasheet(HTML) 4 Page - Fairchild Semiconductor

   
Zoom Inzoom in Zoom Outzoom out
 4 / 5 page
background image
AN-8102
APPLICATION NOTE
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.3
• 4/28/15
4
4. Conclusion
This application note discusses operation and potential
failure modes of HVIC gate drivers. A minimum pulse
width is recommended to prevent abnormal conditions.
VCC
LIN
HIN
GND
VB
HO
VS
LO
Bat1
4
6
7
8
3
1
2
5
FAN7190
0.1µF
Bat2
IN
0.8 V
2.5 V
Tpulse = 80ns
Figure 13.
Short Pulse Width Test Circuit and Pulse
Width Waveform
A short pulse-width test circuit and pulse width waveform
are shown in Figure 13. The timing diagram in Figure 14
shows latch-on and missing output range from 25°C to
125°C temperature.
HIN
HO
Latch-Up
Range
No Output Range
60ns
39ns ~ 54.5ns
19ns~37ns
Figure 14.Timing Diagram Input vs. Output
Normal output signal occurs from 60 ns at 125°C. Take the
worst-case into consideration and give 40% margin for
minimum pulse width. Minimum Pulse Width: 54.5 ns at
125°C x 1.4 times = around 77 ns.
The best solution to address minimum short pulse width
issues
is
determined
by
the
requirements
of
each
application. Each HVIC minimum short pulse width limit is
different because internal circuit and layout are different.
For example; if the HVIC has a half-bridge structure with
one input (e.g., FAN7393), recommended minimum short
pulse width should be 30% longer than dead time. In this
case, effective short pulse width can be counted after it
exceeds the dead time specified in the datasheet (refer to
Table 1).
Table 1. Minimum Short-Pulse Width
Feature
Recommended
Min. Short
Pulse Width
Input
Channel
Output
Channel
Topology
1
1
High-Side Only
77 ns
2
2
Half-Bridge
2 x DT
2
2
High- & Low-
Side, Dual High
Side
77ns
6
6
3-Phase Half-
Bridge
2ⅹDT
1
2
Half-Bridge
2ⅹDT
Notes:
1.
DT is dead time which is referenced to typical value
specified in datasheet.
2.
Recommended min. short pulse width reflects
temperature dependency and the variation between
setting and real dead time.
3.
Some HVIC have built-in advanced input filter to prevent
potential failure mode regarding short pulse input.
Additionally,
judging
from
experimental
test
and
simulation, lower VCC level, such as 12 V, can increase the
possibility of short-pulse latch phenomena. Therefore higher
VCC level, such as 15 V or over 15 V, can mitigate it by
increasing the amplitude of the internal RESET pulse.
For more details, please refer to the corresponding HVIC
datasheet. Minimum pulse time depends on internal
parasitic RC time constants.


Html Pages

1  2  3  4  5 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn