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TLK3132 Datasheet(PDF) 36 Page - Texas Instruments

Part # TLK3132
Description  2-Channel Multi-Rate Transceiver
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLK3132 Datasheet(HTML) 36 Page - Texas Instruments

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TLK3132
SLLS956A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
Table 2-18. PHY_CH_CONTROL_1 (continued)
ADDRESS: 0x10
DEFAULT: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
Logically ORed with SLOOP
When asserted high the data presented at the serial receive interface is looped
back to the serial transmit interface of the same channel via the deserializer, the
serializer and if enabled the PCS function. If 1GX PCS is not enabled, the
16.8
Farend Loopback
RW
incoming data rate must be frequency locked (ppm 0) with REFCLK.
Also referred to as remote loopback.
0 = Farend Loopback is disabled. (Default 1’b0)
1 = Farend loopback is enabled.
A logic 1 enables the PRBS (2^7) verifier in the receive datapath.
16.7
PRBS Verifier Enable
RW
Logically ORed with the PRBSEN pin. (Default 1’b0)
A logic 1 enables the PRBS (2^7) generator in the transmit datapath. Logically
16.6
PRBS Generator Enable
RW
ORed with the PRBSEN pin. (Default 1’b0)
16.5
Channel sync freeze control
When set, freezes last acquired word alignment. (Default 1’b0)
RW
16.4
Test Pattern Generator Enable When high activates the generator selected by bits 16.2:0. (Default 1’b0)
RW
16.3
Test Pattern Verifier Enable
When high activates the verifier selected by bits 16.2:0. (Default 1’b0)
RW
Test Pattern Selection
000 = High Frequency Test Pattern (Default 3’b000)
001 = Low Frequency Test Pattern
16.2:0
Pattern Select
010 = Mixed Frequency Test Pattern
RW
011 = CRPAT Long
100 = CRPAT Short
Others = Reserved
Table 2-19. PHY_CH_CONTROL_2
ADDRESS: 0x11
DEFAULT: 0x3590
BIT(s)
NAME
DESCRIPTION
ACCESS
When written as 1 the settings in 17.14:0 will affect all channels of one device
simultaneously.
17.15
Global write
RW/SC
When written as 0 the settings in 17.14:0 are only valid for the addressed channel.
This value always reads zero.
1 = Causes an override of the sync state of 1000Base-X synchronization state
machine to reflect a “1” in the sync_status (1.2) bit.
17.14
Sync Status Override
RW
0 = Original (normal operation) sync_status value is represented in bit 1.2. (Default
1’b0)
When asserted, allows the ten bits of data given to the parallel side of the
SERDES TX macro to be flipped. This is normally set since the SERDES transmits
17.13
TX PMA Bit Order
RW
MSB first, and the 1000Base-X standard requires LSB to be transmitted first. For
standard based operation, the customer may leave this bit alone. (Default 1’b1)
When asserted, allows the ten bits of data received from the parallel side of the
SERDES RX macro to be flipped. This is normally set since the SERDES receives
17.12
RX PMA Bit Order
RW
MSB first, and the 1000Base-X standard requires LSB to be received first. For
standard based operation, the customer may leave this bit alone. (Default 1’b1)
1 = Overrides Loss of signal (LOS) status coming from SERDES. Synchronization
17.11
LOS Override
turned on irrespective of LOS status
RW
0 = Synchronization depends on LOS status. (Default 1’b0)
1 = Clock Tolerance Compensation on receive datapath is enabled (Default 1’b1)
17.10
CTC enable
RW
0 = Clock Tolerance Compensation on receive datapath is disabled
1 = Sets the device in full DDR mode (NBID/TBID modes)
17.9
Full DDR mode
RW
0 = Disables full DDR mode (Default)
1 = Enables RX_CLK out (Default 1’b1)
17.8
RCLK out enable
0 = Disables RX_CLK out.
RW
RX_CLK will be low when this bit is de-asserted
1 = Enables comma detection (Default 1’b1)
17.7
Comma enable
RW
0 = Disables comma detection
1 = Enables FC_PH overlay detection. This is needed in 1x/2x Fiber channel mode
17.6
FC enable
to allow proper detection of EOF 8B/10B disparity
RW
0 = Disables FC_PH overlay detection (Default 1’b0)
36
Detailed Description
Copyright © 2008–2009, Texas Instruments Incorporated
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