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LP8728-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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LP8728-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 25 page LP8728-Q1 SNVS972B – AUGUST 2013 – REVISED DECEMBER 2014 www.ti.com 6.5 Electrical Characteristics (1) (2) Unless otherwise noted, VIN = 5 V, typical values apply for TA = 25°C, and minimum/maximum limits apply over junction temperature range, TJ = –40°C to 125°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Shutdown supply current into power ISHDN EN_Bx = 0 V 1 6 μA connections IOP Operating current All buck-converters active, IOUT = 0 mA 20 mA LOGIC INPUTS (EN_Bx, DEFSEL) VIL Input low level 0.4 V VIH Input high level 1.6 V EN_Bx and DEFSEL internal pull- RPD_DI 300 520 820 k Ω down resistance TH_MIN Minimum EN_Bx high time 1 ms TL_MIN Minimum EN_Bx low time 10 µs LOGIC OUTPUTS (PG_Bx) VOL Output low level ISINK = 3 mA 0.4 V RPU Recommended pull-up resistor 10 k Ω BUCK CONVERTERS VOUT1 Output voltage for Buck 1 Fixed voltage 3.3 V VOUT2 Output voltage for Buck 2 Fixed voltage 1.25 V DEFSEL = 1 2.65 VOUT3 Output voltage for Buck 3 V DEFSEL = 0 1.8 VOUT4 Output voltage for Buck 4 Fixed voltage 1.8 V VFB_Bx Output voltage accuracy –3% 3% Line regulation 4.5 V ≤ VIN_Bx ≤ 5.5 V ILOAD = 10 mA 3 mV ΔVOUT Load regulation VIN = 5 V 100 mA ≤ ILOAD ≤ 900 mA 3 mV DC load IOUT Output current 1000 mA TA = 25°C. FSW Switching frequency 3.03 3.2 3.37 MHz GBW Gain bandwidth 300 kHz ILIMITP High side switch current limit 1200 1500 1800 mA ILIMITN Low side switch current limit Reverse current 500 mA RDSONP Pin-pin resistance for PFET IOUT = 200 mA 210 300 m Ω RDSONN Pin-pin resistance for NFET IOUT = 200 mA 140 240 m Ω ILK_SW Switch pin leakage current VOUT = 1.8V 1 µA Pull-down resistor from FB_Bx pin to Only active when converter disabled. RPD_FB 40 70 100 Ω GND All limits apply for TA = 25°C. KRAMP Slew rate control DEFSEL from 0 to 1 10 mV/µs Time from first EN_Bx high to start of TSTART Start-up time 420 µs switching KSTART Soft-start VOUT slew rate 18 mV/µs VOLTAGE MONITORING Power good threshold for voltage rising 93.5% 96% 98% VPG Power good threshold voltage Power good threshold for voltage falling 91% 93% 95% Voltage monitored on AVDD Pin, V 5.5 5.7 5.9 Input overvoltage protection trigger voltage rising VOVP point Hysteresis 80 mV (1) All voltage values are with respect to network ground terminal. (2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 5 V and TJ = 25°C. 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LP8728-Q1 |
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