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5962-0522101VXC Datasheet(PDF) 6 Page - Texas Instruments

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Part # 5962-0522101VXC
Description  TLK2711-SP 1.6-Gbps to 2.5-Gbps Class V Transceiver
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

5962-0522101VXC Datasheet(HTML) 6 Page - Texas Instruments

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6
TLK2711-SP
SGLS307O – JULY 2006 – REVISED MARCH 2016
www.ti.com
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Copyright © 2006–2016, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
(2)
Internal 10-k
Ω pulldown
LOOPEN
22
I(2)
Loop enable. When LOOPEN is active high, the internal loopback path is activated. The transmitted
serial data is directly routed internally to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-
impedance state during the loopback test. LOOPEN is held low during standard operational state,
with external serial outputs and inputs active.
PRE
60
I(2)
Preemphasis control. Selects the amount of preemphasis to be added to the high-speed serial
output drivers. Left low or unconnected, 5% preemphasis is added. Pulled high, 20% preemphasis
is added.
PRBSEN
27
I(2)
PRBS test enable. When asserted high, results of pseudo-random bit stream (PRBS) tests can be
monitored on the RKLSB pin. A high on RKLSB indicates that valid PRBS is being received.
RKLSB
30
O
K-code indicator/PRBS test results. When RKLSB is asserted high, an 8-bit/10-bit K code was
received and is indicated by data bits RXD0 through RXD7. When RKLSB is asserted low, an 8-
bit/10-bit D code is received and is presented on data bits RXD0 through RXD7. When PRBSEN is
asserted high, this pin is used to indicate status of the PRBS test results (high = pass).
RKMSB
31
O
K-code indicator. When RKMSB is asserted high an 8-bit/10-bit K code was received and is
indicated by data bits RXD8 through RXD15. When RKMSB is asserted low an 8-bit/10-bit D code
was received and is presented on data bits RXD8 through RXD15. If the differential signal on RXN
and RXP drops below 200 mV, RXD0–RXD15, RKLSB, and RKMSB are all asserted high. When
device is disabled (ENABLE = L), RKMSB will output the status of LOS. Active low = LOS detected.
RXCLK
RX_CLK
43
O
Recovered clock. Output clock that is synchronized to RXD0 through RXD9, RKLSB, and RKMSB.
RXCLK is the recovered serial data rate clock divided by 20. RXCLK is held low during power-on
reset.
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD8
RXD9
RXD10
RXD11
RXD12
RXD13
RXD14
RXD15
54
53
52
49
48
47
46
44
42
41
39
38
37
36
33
32
O
Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the
protocol device, synchronized to RXCLK. The data is valid on the rising edge of RXCLK as shown
in Figure 10. These pins are in high-impedance state during power-on reset.
DINRXN
DINRXP
56
57
I
Serial receive inputs. RXP and RXN together are the differential serial input interface from a copper
or an optical I/F module.
TESTEN
28
I(2)
Test mode enable. This pin should be left unconnected or tied low.
TKLSB
23
I(2)
K-code generator (LSB). When TKLSB is high, an 8-bit/10-bit K code is transmitted as controlled by
data bits TXD0 through TXD7. When TKLSB is low, an 8-bit/10-bit D code is transmitted as
controlled by data bits TXD0 through TXD7.
TKMSB
21
I(2)
K-code generator (MSB). When TKMSB is high, an 8-bit/10-bit K code is transmitted as controlled
by data bits TXD8 through TXD15. When TKMSB is low, an 8-bit/10-bit D code is transmitted as
controlled by data bits TXD8 through TXD15.
TXCLK
GTX_CLK
8
I
Reference clock. TXCLK is a continuous external input clock that synchronizes the transmitter
interface signals TKMSB, TKLSB, and TXD0–TXD15. The frequency range of TXCLK is 80 to 125
MHz. The transmitter uses the rising edge of this clock to register the 16-bit input data TXD0
through TXD15 for serialization.


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