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TLV2352MJG Datasheet(PDF) 1 Page - Texas Instruments |
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TLV2352MJG Datasheet(HTML) 1 Page - Texas Instruments |
1 / 24 page Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TLV2352, TLV2352Y LinCMOS ™ DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS SLCS011B – MAY 1992 – REVISED MARCH 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Wide Range of Supply Voltages 2 V to 8 V D Fully Characterized at 3 V and 5 V D Very-Low Supply-Current Drain 120 µA Typ at 3 V D Output Compatible With TTL, MOS, and CMOS D Fast Response Time . . . 200 ns Typ for TTL-Level Input Step D High Input Impedance ...1012 Ω Typ D Extremely Low Input Bias Current 5 pA Typ D Common-Mode Input Voltage Range Includes Ground D Built-In ESD Protection description The TLV2352 consists of two independent, low-power comparators specifically designed for single power-supply applications and operates with power-supply rails as low as 2 V. When powered from a 3-V supply, the typical supply current is only 120 µA. The TLV2352 is designed using the Texas Instruments LinCMOS ™ technology and therefore features an extremely high input impedance (typically greater than 1012 Ω), which allows direct interfacing with high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic wired-AND relationships. The TLV2352I is fully characterized at 3 V and 5 V for operation from – 40 °C to 85°C. The TLV2352M is fully characterized at 3 V and 5 V for operation from – 55 °C to 125°C. The TLV2352 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a 1000-V ESD rating using Human Body Model testing. However, care should be exercised in handling this device as exposure to ESD may result in degradation of the device parametric performance. AVAILABLE OPTIONS PACKAGED DEVICES CHIP TA VIO max at 25 °C SMALL OUTLINE (D)† CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP (PW)‡ PLASTIC DIP (U) CHIP FORM (Y) –40 °C to 85 °C 5 mV TLV2352ID — — TLV2352IP TLV2352IPWLE — TLV2352Y –55 °C to 125 °C 5 mV — TLV2352MFK TLV2352MJG — — TLV2352MU TLV2352Y † The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLV2352IDR). ‡ The PW packages are only available left-ended taped and reeled (e.g., TLV2352IPWLE) These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LinCMOS is a trademark of Texas Instruments Incorporated. OUT IN + IN – symbol (each comparator) On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. |
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