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ICPL2631 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. ICPL2631
Description  DUAL CHANNEL, HIGH CMR, VERY HIGH SPEED OPTICALLY COUPLED ISOLATOR LOGIC GATE OUTPUT
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ICPL2631 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

   
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SWITCHING SPECIFICATIONS AT T
A = 25°C ( VCC = 5V, IF = 7.5mA Unless otherwise noted )
PARAMETER
SYM DEVICE
MIN TYP MAX UNITS TEST CONDITION
Propagation Delay Time
to Logic Low at Output
t
PHL
55
75
ns
R
L = 350Ω, CL = 15pF
( fig 1 )( note2 )
Propagation Delay Time
to Logic High at Output
t
PLH
45
75
ns
R
L = 350Ω, CL = 15pF
( fig 1 )( note3 )
Common Mode Transient
Immunity at Logic High
CM
H
ICPL2630
10000
V/
µs
I
F = 0mA, VCM = 50VPP
Level Output ( fig 2 )( note7 )
ICPL2631
1000 10000
V/
µs
R
L= 350Ω,VOH= 2Vmin.
Common Mode Transient
Immunity at Logic Low
CM
L
ICPL2630
-10000
V/
µs
V
CM= 50VPP
Level Output ( fig 2 )( note8 )
ICPL2631 -1000 -10000
V/
µs
R
L=350Ω,VOL=0.8Vmax.
NOTES:-
1
Bypassing of the power supply line is required, with a 0.01
µF ceramic disc capacitor adjacent to
each isolator. The power supply bus for the isolator(s) should be seperate from the bus for any
active loads. Otherwise a larger value of bypass capacitor (up to 0.1
µF) may be needed to supress
regenerative feedback via the power supply.
2
The t
PHL
propagation delay is measured from the 3.75 mA level Low to High transition of the input
current pulse to the 1.5V level on the High to Low transition of the output voltage pulse.
3
The t
PLH propagation delay is measured from the 3.75mA level High to Low transition of the input
current pulse to the 1.5V level on the Low to High transition of the output voltage pulse.
4
Device considered a two terminal device; pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7
and 8 shorted together.
5
Each channel.
6
Measured between pins 1 and 2 shorted together and pins 3 and 4 shorted together.
7
CM
H is the maximum tolerable rate of rise of the common mode voltage to assure that the output
will remain in a high logic state (ie Vout > 2.0V).
8
CM
L is the maximum tolerable rate of fall of the common mode voltage to assure that the output
will remain in a low logic state (ie Vout < 0.8V)
DB92601-AAS/A1
9/10/00
FIG.1 SWITCHING TEST CIRCUIT
2
I
F Monitor
0
I
F
V
O
1.5V
100
1.5V
5V
t
PHL
t
PLH
V
OL
R
L
V
O
C
L = 15pF
8
7
6
5
PULSE
GENERATOR
Z
O = 50Ω
t
r = 5ns
I
F
1
4
3
5V


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