Electronic Components Datasheet Search |
|
LP3950 Datasheet(PDF) 11 Page - Texas Instruments |
|
|
LP3950 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 38 page start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop ack from slave ack from slave ack from slave SCL SDA start Id = 36h w ack addr = 02h ack ack DGGUHVV K¶02 data stop ADR6 bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 MSB LSB 0 1 1 0 1 1 0 C SLAVE address (chip address) I 2 SDA SCL S P START condition STO P condition LP3950 www.ti.com SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013 I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transition from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, the I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. Figure 7. Start and Stop Conditions TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3950 address is 50'h or 51'h. The selection of the address is done by connecting SI pin to VDDIO (51 hex) or GND (50 hex). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. Figure 8. I2C Chip Address w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = chip address, 50'h or 51'h for LP3950. Figure 9. I2C Write Cycle Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LP3950 |
Similar Part No. - LP3950 |
|
Similar Description - LP3950 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |