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TLC34076-85FN Datasheet(PDF) 36 Page - Texas Instruments |
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TLC34076-85FN Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 69 page  2–20 The HSYNC and VSYNC inputs are used for both the VGA pass-through and normal modes. When the application uses both VGA pass-through and normal modes, an external multiplexer is needed to select HSYNC and VSYNC between the VGA pass-through mode and the normal mode. The MUXOUT signal is designed for this purpose (see Sections 2.10 and 2.11). The HSYNC, VSYNC, and BLANK signals have internal pipeline delays to align with the data at the DAC outputs. Due to the sample and latch timing delay, it is possible to have active SCLK pulses after the BLANK input becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch delay need to be carefully reviewed and programmed (see Section 2.3 and Figures 2–2 and 2–3 for more details). As shown in Figure 2– 6 for the IOG DAC output, active HSYNC and VSYNC signals turn off the sync current source (after the pipeline delay) independent of the BLANK signal level. In real applications, HSYNC and VSYNC should only be active (low) when BLANK is active (low). To alter the polarity of the HSYNCOUT and VSYNCOUT outputs in the normal modes, the MPU must set or clear the corresponding bits in the General Control register (see subsection 2.11.1). Again, these two bits affect only the normal modes, not the VGA pass-through mode. These bits default to 1. 2.9 Split Shift Register Transfer VRAMs and Special Nibble Mode The following paragraphs describe the operation of the split shift register when effecting a transfer from the VRAMs, and the use of the special nibble mode. The special nibble mode provides a variation of the 4-bit pixel mode with a 16-bit bus width. 2.9.1 Split Shift Register Transfer VRAMs The TLC34076 directly supports split shift register transfer (SSRT) VRAMs. In order to allow the VRAMs to perform a split shift-register transfer, an extra SCLK cycle must be inserted during the Blank sequence. This is initiated when the SSRT enable bit is set to 1, the SNM bit is reset to 0 , and a rising edge on the SFLAG/NFLAG input terminal is detected. An SCLK pulse is generated within 20 ns of the rising edge of the SFLAG/NFLAG signal. A minimum 15-ns high logic level duration is provided to satisfy all of the 15-ns VRAM requirements. By controlling the SFLAG/NFLAG rise time, the delay time from the rising edge of the VRAM TRG signal to SCLK can be satisfied. The relationship between the SCLK, SFLAG/NFLAG, and BLANK signals is shown in Figure 2-9. SCLK Input SFLAG/NFLAG Register Bit 2) (General Control SSRT Enable BLANK Figure 2–9. Relationship Between SFLAG/NFLAG, BLANK, and SCLK When SFLAG/NFLAG is designed as an R-S latch set by split shift register transfer timing and reset by BLANK going high, the delay from BLANK high to SFLAG/NFLAG low cannot exceed one-half of a SCLK cycle; otherwise, the SCLK generation logic may fail. |
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