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TLC34076-85FN Datasheet(PDF) 24 Page - Texas Instruments |
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TLC34076-85FN Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 69 page  2–8 and Regular Shift Register Transfer SCLK Between Split Shift-Register SCLK at Input Terminal Pixel Data Pipeline Delay) Before DOTCLK (Internal Signal Blank for Data Latch) (Internal Signal Load at Input Terminal BLANK of Pixel Data Latch Last Group of Pixel Data Latch First Group 1st Group of Pixel Data Group 2nd Group 3rd Group 4th Group 5th Group 6th Group Last VCLK SFLAG/NFLAG NOTE A: Either the SSRT function is disabled (general-control register bit 2 = 0), or the SFLAG/NFLAG input is held low when the SSRT function is enabled (general-control register bit 2 = 1). Figure 2–5. SCLK/VCLK Control Timing (SSRT Enabled, SCLK Frequency = 4 × VCLK Frequency) 2.4 Multiplexing Scheme The TLC34076 offers a highly versatile multiplexing scheme as illustrated in Table 2–6. The on-chip multiplexing allows the system to be reconfigured to the amount of RAM available. For example, when only 256K bytes of memory are available, an 800-by-600 resolution mode with four bit-planes (4 bits per pixel) can be implemented using an 8-bit wide pixel bus. If, at a later date, another 256K bytes are added to another 8 bits of the pixel bus, the user has the option of using eight bit-planes at the same resolution or four bit-planes at a 1024 × 768 resolution. When an additional 512K bytes are added to the remaining 16 bits of the pixel bus, the user has the option of eight bit-planes at 1024 × 768 resolution or four bit-planes at 1280 × 1024 resolution. All the above can be achieved without any hardware modification and without any increase in the speed of the pixel bus. |
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