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TLC32044CFN Datasheet(PDF) 12 Page - Texas Instruments

Part No. TLC32044CFN
Description  VOICE-BAND ANALOG INTERFACE CIRCUITS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLC32044CFN Datasheet(HTML) 12 Page - Texas Instruments

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TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F − MARCH 1988 − REVISED MAY 1995
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
secondary DX serial communication protocol
x x |
← to TA register → | x x | ← to RA register → |
0
0
d13 and d6 are MSBs (unsigned binary)
x |
← to TA’ register → | x | ← to RA’ register → |
0
1
d14 and d7 are 2’s complement sign bits
x |
← to TB register → | x | ← to RB register → |
1
0
d14 and d7 are MSBs (unsigned binary)
x
x
x
x
x
x
d9
x
d7
d6
d5
d4
d3
d2 1
1
Control
Register
d2 = 0/1 deletes/inserts the A/D high-pass filter
d3 = 0/1 disables/enables the loopback function
d4 = 0/1 disables/enables the AUX IN + and AUX IN −
d5 = 0/1 asynchronous/synchronous transmit and receive sections
d6 = 0/1 gain control bits (see gain control section)
d7 = 0/1 gain control bits (see gain control section)
d9 = 0/1 delete/insert on-board second-order (sin x) / x correction filter
reset function
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
initializes all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on RESET initializes the AIC registers to provide an 8-kHz A/D and D/A conversion rate
for a 5.184 MHz master clock input signal. The AIC, except the control register, is initialized as follows (see AIC
DX data word format section):
REGISTER
INITIALIZED
REGISTER
VALUE (HEX)
TA
9
TA’
1
TB
24
RA
9
RA’
1
RB
24
The control register bits are reset as follows (see AIC DX data word format section):
d9 = 1, d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit and
receive sections are configured to operate synchronously and the user wishes to program different conversion
rates, only the TA, TA’, and TB register need to be programmed, since both transmit and receive timing are
synchronously derived from these registers (see the terminal functions table and AIC DX word format sections).
The circuit shown in Figure 1 provides a reset on power up when power is applied in the sequence given under
power-up sequence. The circuit depends on the power supplies reaching their recommended values a minimum
of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
VCC +
VCC −
RESET
200 k
0.5
µF
TLC32044/TLC32045
5 V
−5 V
Figure 1. Power-Up Reset


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