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TLC32044CFN Datasheet(PDF) 4 Page - Texas Instruments

Part No. TLC32044CFN
Description  VOICE-BAND ANALOG INTERFACE CIRCUITS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLC32044CFN Datasheet(HTML) 4 Page - Texas Instruments

 
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TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F − MARCH 1988 − REVISED MAY 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
EODX
11
O
End of data transmit. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 (SMJ320) serial port to the AIC.
EODX can be used to interrupt a microprocessor upon the completion of serial communications. Also,
EODX can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external
FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel
shift registers. During the byte-mode timing, EODX goes low after the first byte has been transmitted from
the TMS320 (SMJ320) serial port to the AIC and is kept low until the second byte has been transmitted. The
DSP can use this low-going signal to differentiate between the two bytes as to which is first and which is
second.
FSR
4
O
Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description,
FSR is held low during bit transmission. When FSR goes low, the TMS320 (SMJ320) serial port begins
receiving bits from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes
low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after
secondary communications.
FSX
14
O
Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
FSX
14
O
Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
AIC via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description,
FSX is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration diagrams).
AIC via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description,
FSX is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration diagrams).
IN +
26
I
Noninverting input to analog input amplifier stage
IN −
25
I
Inverting input to analog input amplifier stage
MSTR CLK
6
I
Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals
are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal
Timing Configuration diagram).
OUT +
22
O
Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended configuration.
OUT −
21
O
Inverting output of analog output power amplifier. OUT− is functionally identical with and complementary
to OUT +.
REF
8
I/O
Internal voltage reference. An internal reference voltage is brought out on REF. An external voltage
reference can also be applied to REF.
RESET
2
I
Reset function. RESET is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. A reset
initiates serial communications between the AIC and DSP. A reset initializes all AIC registers including the
control register. After a negative-going pulse on RESET, the AIC registers are initialized to provide an 8-khz
data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA’
and RA’, are reset to 1. The control register bits are reset as follows (see AIC DX data word format section):
d9 = 1, d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1.
This initialization allows normal serial-port communication to occur between the AIC and DSP.
SHIFT CLK
10
O
Shift clock. SHIFT CLK is obtained by dividing the master clock signal frequency by four. SHIFT CLK is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial
Port Timing and Internal Timing Configuration diagrams).
VDD
7
Digital supply voltage, 5 V
±5%
VCC +
20
Positive analog supply voltage, 5 V
±5%
VCC −
19
Negative analog supply voltage, − 5 V
±5%


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