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TLC32044CFN Datasheet(PDF) 27 Page - Texas Instruments

Part No. TLC32044CFN
Description  VOICE-BAND ANALOG INTERFACE CIRCUITS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLC32044CFN Datasheet(HTML) 27 Page - Texas Instruments

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TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F − MARCH 1988 − REVISED MAY 1995
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
serial port — AIC output signals
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc(SCLK)
Shift clock (SCLK) cycle time
380
ns
tf(SCLK)
Shift clock (SCLK) fall time
50
ns
tr(SCLK)
Shift clock (SCLK) rise time
50
ns
Shift clock (SCLK) duty cycle
45
55
%
td(CH-FL)
Delay from SCLK
↑ to FSR/FSX↓
CL = 50 pF
52
ns
td(CH-FH)
Delay from SCLK
↑ to FSR/FSX↑
CL = 50 pF
52
ns
td(CH-DR)
DR valid after SCLK
90
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in word mode
90
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in word mode
90
ns
tf(EODX)
EODX fall time
15
ns
tf(EODR)
EODR fall time
15
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in byte mode
100
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in byte mode
100
ns
td(MH-SL)
Delay from MSTR CLK
↑ to SCLK↓
65
ns
td(MH-SH)
Delay from MSTR CLK
↑ to SCLK↑
65
ns
serial port — AIC output signals, TLC32044M
MIN
TYP
MAX
UNIT
tc(SCLK)
Shift clock (SCLK) cycle time
400
ns
tf(SCLK)
Shift clock (SCLK) fall time
50
ns
tr(SCLK)
Shift clock (SCLK) rise time
50
ns
Shift clock (SCLK) duty cycle
50
%
td(CH-FL)
Delay from SCLK
↑ to FSR/FSX↓
260
ns
td(CH-FH)
Delay from SCLK
↑ to FSR/FSX↑
260
ns
td(CH-DR)
DR valid after SCLK
316
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in word mode
280
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in word mode
280
ns
tf(EODX)
EODX fall time
15
ns
tf(EODR)
EODR fall time
15
ns
td(CH-EL)
Delay from SCLK
↑ to EODX/EODR↓ in byte mode
100
ns
td(CH-EH)
Delay from SCLK
↑ to EODX/EODR↑ in byte mode
100
ns
td(MH-SL)
Delay from MSTR CLK
↑ to SCLK↓
65
ns
td(MH-SH)
Delay from MSTR CLK
↑ to SCLK↑
65
ns
Typical values are at TA = 25°C.


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