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TLC2551IDGK Datasheet(PDF) 7 Page - Texas Instruments

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Part No. TLC2551IDGK
Description  5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLC2551IDGK Datasheet(HTML) 7 Page - Texas Instruments

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TLC2551, TLC2552, TLC2555
5-V, LOW-POWER, 12-BIT, 175/360 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D – MARCH 2000 – REVISED MAY 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
using CS as the FS input
When interfacing the TLC2551 with the TMS320 DSP, the FSR signal from the DSP may be connected to the
CS input if this is the only device on the serial port. This connection saves one output terminal from the DSP.
(Output data changes on the falling edge of SCLK. This is the default configuration for the TLC2552 and
TLC2555).
SCLK and conversion speed
The SCLK input can range in frequency from 100 kHz to 20 MHz. The required number of conversion clocks
is 14. The conversion clock for the ADC is SCLK/2 which translates to 28 SCLK cycles to perform a conversion.
For a 15-MHz SCLK, the minimum total cycle time is given by: 16x(1/15 M)+14x(1/7.5 M)+1 SCLK = 3.0
µs. An
additional SCLK is added to account for the required CS or FS high time. These times specify the minimum cycle
time for an active CS or FS signal. If violated, the conversion terminates, invalidating the next data output cycle.
Table 1 gives the maximum SCLK frequency for a given operational mode.
control via pin 1 (CS, SPI interface)
All devices are compatible with this mode of operation. A falling CS initiates the cycle. (For TLC2551, the FS
input is tied to VDD.) CS remains low for the entire cycle time (sample + convert + 1 SCLK) and can then be
released.
NOTE:
IMPORTANT: A single SCLK is required whenever CS is high.
control via pin 1 (CS, DSP interface)
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the
CS input of the ADC. A falling edge on the CS input initiates the cycle. (For TLC2551, the FS input can be tied
to VDD, although better performance can be achieved by using the FS input for control. Refer to the control via
pin 1 and pin 7 (CS and FS or FS only, DSP interface) section. The CS input should remain low for the entire
cycle time (sample + convert + 1 SCLK) and can then be released.
NOTE:
IMPORTANT: A single SCLK is required whenever CS is high. This requirement is usually of little
consequence since SCLK is normally always present when interfacing with a DSP.
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)
Only the TLC2551 is compatible with this mode of operation. The CS input to the ADC can be controlled via a
general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the
ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS
edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and
FS inputs should remain low for the entire cycle time (sample + convert + 1 SCLK) and can then be released.
reference voltage
An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the
analog inputs to produce a full-scale reading. The value of VREF and the analog input must not exceed the
positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output
is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal
to or lower than GND.
powerdown and powerup
Autopower down is built into these devices in order to reduce power consumption. The actual power savings
depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors.
Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some
power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 8
µA
within 0.5
µs. To achieve the lowest power-down current (deep powerdown) of 1 µA requires 2-ms inactive time
between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately
at the next falling edge of CS or the rising edge of FS.


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