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IDT821024PP Datasheet(PDF) 11 Page - Integrated Device Technology

Part # IDT821024PP
Description  QUAD NON-PROGRAMMABLE PCM CODEC
Download  13 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT821024PP Datasheet(HTML) 11 Page - Integrated Device Technology

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11
INDUSTRIAL TEMPERATURE RANGE
IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC
TIMING CHARACTERISTICS
Clock
Parameter
Description
Min
Typ
Max
Units
Test Conditions
t1
PCLK Duty Cycle
40
60
%
PCLK=512kHz to 8.192MHz
t2
PCLK Rise and Fall Time
25
ns
PCLK=512kHz to 8.192MHz
t3
MCLK Duty Cycle
40
60
%
MCLK=2.048Hz,4.096MHz
or 8.192MHz
t4
MCLK Rise and Fall Time
15
ns
MCLK=2.048Hz,4.096MHz
or 8.192MHz
t5
PCLK Clock Period
244
ns
PCLK=512kHz to 8.192MHz
Transmit
Parameter
Description
Min
Typ
Max
Units
Test Conditions
t11
Data Output Delay Time (for Short
Frame Sync Mode)
5
70
ns
t12
Data Hold Time
5
70
ns
t13
Data Delay to High-Z
50
220
t5+70
ns
t14
Frame sync Hold Time
50
ns
t15
Frame sync High Setup Time
55
t5-50
ns
t16
TSC Enable Delay Time(for Short
Frame Sync Mode)
5
80
ns
t17
TSC Disable Delay Time
50
220
t5+70
ns
t18
Data Output Delay Time(for Long
Frame Sync Mode)
5
40
ns
t19
TSC Enable Delay Time(for Long
Frame Sync Mode)
5
40
ns
t21
Receive Data Setup Time
25
ns
t22
Receive Data Hold Time
5
ns
Figure 2. MCLK Timing
Note: Timing parameter t13 is referenced to a high-impedance state.
MCLK
t4
t4


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