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TLC548C Datasheet(PDF) 5 Page - Texas Instruments

Part # TLC548C
Description  8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLC548C Datasheet(HTML) 5 Page - Texas Instruments

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TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VOH
High-level output voltage
VCC = 4.75 V, IOH = – 360 µA
2.4
V
VOL
Low-level output voltage
VCC = 4.75 V, IOL = 3.2 mA
0.4
V
IOZ
High impedance off state output current
VO = VCC,
CS at VCC
10
µA
IOZ
High-impedance off-state output current
VO = 0,
CS at VCC
–10
µA
IIH
High-level input current, control inputs
VI = VCC
0.005
2.5
µA
IIL
Low-level input current, control inputs
VI = 0
– 0.005
– 2.5
µA
II( )
Analog channel on-state input current during sample
Analog input at VCC
0.4
1
µA
II(on)
gg
cycle
Analog input at 0 V
– 0.4
–1
µA
ICC
Operating supply current
CS at 0 V
1.8
2.5
mA
ICC + Iref
Supply and reference current
Vref+ = VCC
1.9
3
mA
Ci
Input capacitance
Analog inputs
7
55
pF
Ci
Input capacitance
Control inputs
5
15
pF
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC548 or 1.1 MHz for TLC549
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC548
TLC549
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
MIN
TYP†
MAX
UNIT
EL
Linearity error
See Note 6
±0.5
±0.5
LSB
EZS
Zero-scale error
See Note 7
±0.5
±0.5
LSB
EFS
Full-scale error
See Note 7
±0.5
±0.5
LSB
Total unadjusted error
See Note 8
±0.5
±0.5
LSB
tconv
Conversion time
See Operating Sequence
8
17
12
17
µs
Total access and conversion time
See Operating Sequence
12
22
19
25
µs
ta
Channel acquisition time (sample cycle)
See Operating Sequence
4
4
I/O
clock
cycles
tv
Time output data remains
valid after I/O CLOCK
10
10
ns
td
Delay time to data output valid
I/O CLOCK
200
400
ns
ten
Output enable time
1.4
1.4
µs
tdis
Output disable time
150
150
ns
tr(bus)
Data bus rise time
See Figure 1
300
300
ns
tf(bus)
Data bus fall time
300
300
ns
† All typicals are at VCC = 5 V, TA = 25°C.
NOTES:
6. Linearity error is the deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
8. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.


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