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TLC320AD56CPT Datasheet(PDF) 39 Page - Texas Instruments

Part No. TLC320AD56CPT
Description  Sigma-Delta Analog Interface Circuit
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLC320AD56CPT Datasheet(HTML) 39 Page - Texas Instruments

 
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A–1
Appendix A
Register Set
Bits D12 through D8 in a secondary serial communication comprise the address of the register that is written
with the data carried in D7 through D0. D13 determines a read or write cycle to the addressed register. When
low, a write cycle is selected.
Table A–1 shows the register map.
Table A–1. Data and Control Registers
REGISTER NO
BITS
REGISTER NAME
REGISTER NO.
D15
D14
D13
D12
D11
D10
D9
D8
REGISTER NAME
0
0
0
0
0
0
0
0
0
No operation
1
0
000000
1
Control 1
2
0
0
0
0
0
0
1
0
Control 2
Table A–2. Control 1 Register
BITS
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
1
Software reset
0
Software reset not asserted
1
Software power down (analog and filters)
0
Software power down (not asserted)
1
Select AUXP and AUXM
0
Select INP and INM
0
Select INP and INM for monitor
1
Select AUXP and AUXM for monitor
1
1
Monitor amp gain = – 18 dB (see Note B)
1
0
Monitor amp gain = – 8 dB (see Note B)
0
1
Monitor amp gain = 0 dB (see Note B)
0
0
Monitor amp mute
1
Digital loopback asserted
0
Digital loopback not asserted
1
16-bit mode (hardware secondary requests)
0
Not 16-bit mode (software secondary requests)
NOTES:
A. Default value: 00000000
B. These gains are for a single-ended input. The gain is 6 dB lower with a differential input.
The software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write
a zero to end the master reset operation. Writing 0s to the reserved bits is suggested.


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