TLC320AD50C datasheet(26/57 Pages) TI1

Part #	TLC320AD50C

Description	SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

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2–11

2.8

Frame-Sync Function for TLC320AD52C

The frame-sync function for TLC320AD52C is very similar to that of the TLC320AD50C except the following:

1.

TLC320AD52C can support only one slave.

2.

The FSD terminal function can be disabled for TLC320AD52C by programming bit D2 in control 2 register.

3.

The FSD value loaded into control 3 register must be multiplied by 2 to obtain the actual number of SCLKs

for the delay.

For example, if FSD register (control register 3) is programmed with 49H, it means that the TLC320AD52C has one

slave and the FSD terminal has 18 SCLKs delay after master primary FS output. See Figure 2–14.

FS

FSD

256 SCLKs

MP

SP

MS

SS

MP

128 SCLKs

Delay is

≥18

SCLKs

(See Note A)

NOTE A: Minimum SCLK delay number in FSD register is 9. This means that a delay of at least 18 SCLKs is required for proper operation of the

TLC320AD52C.

Figure 2–14. Master Device FS and FSD Output After Control 3 Register

Is Programmed With 49H

2.9

Multiplexed Analog Input and Output

The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta modulator.

The performance of the AUX channel is similar to the normal input channel. A single-pole antialias filter must be

connected to INP and INM (also AUXP and AUXM, if used). If an RC is used for the single-pole filter (Figure 2–15)

the value of R should not be greater that 1 k

Ω. The gain of the input amplifiers is set through the control register 4.

C

IN +

R

INP

C

IN –

R

INM

NOTES: A. The bandwidth of this RC antialias is determined by: (f0 = 1/(2π RC))

B. AUXP and AUXM need to be connected to AVSS if not used.

C. Bandwidth of the antialias filter can be 4

× fs.

D. The input signal must have AVDD/2 dc or it must be ac-coupled.

Figure 2–15. RC Antialias Filter

To produce the best possible common-mode rejection of unwanted signal performance, the analog signal is

processed differentially until it is converted to digital data. The signal applied to the terminals INM and INP should

be differential to preserve the device specifications. As much as 6 dB of signal level will be lost if the single-ended

input is used directly. The signal source driving the analog inputs (INP and INM or AUXP and AUXM) should have

a low source impedance for best low-noise performance and accuracy.

To obtain maximum dynamic range, the signal should be ac-coupled to the input terminal. The analog input signal

is self-biased to the midsupply voltage if the monitor-amplifier input source is selected as the same source for the

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