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TLC27L2BCDRG4 Datasheet(PDF) 15 Page - Texas Instruments

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Part No. TLC27L2BCDRG4
Description  LinCMOSE PRECISION DUAL OPERATIONAL AMPLIFIERS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLC27L2BCDRG4 Datasheet(HTML) 15 Page - Texas Instruments

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TLC27L2, TLC27L2A, TLC27L2B, TLC27L7
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(see Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(d) f > BOM
(c) f = BOM
(b) BOM > f > 100 kHz
(a) f = 100 kHz
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS high-volume, short-test-time
environment. Internal capacitances are inherently higher in CMOS devices and require longer test times than
their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and
lower temperatures.


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