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TLC2254IN Datasheet(PDF) 46 Page - Texas Instruments

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Part No. TLC2254IN
Description  Advanced LinCMOS RAIL-TO-RAIL VERY LOW-POWER OPERATIONAL AMPLIFIERS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLC2254IN Datasheet(HTML) 46 Page - Texas Instruments

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TLC225x, TLC225xA
Advanced LinCMOS
 RAIL-TO-RAIL
VERY LOW-POWER OPERATIONAL AMPLIFIERS
SLOS176D – FEBRUARY 1997 – REVISED MARCH 2001
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLC225x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56
and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 60) improves the gain and phase margins
when driving large capacitive loads. Figure 56 and Figure 57 show the effects of adding series resistances of
10
Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first is that it adds
a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the
output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
∆φ
m1 + tan
–1
2
× π× UGBW × R
null ×
C
L
Where :
(1)
∆φ
m1 + Improvement in phase margin
UGBW
+ Unity-gain bandwidth frequency
R
null + Output series resistance
C
L + Load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To
use equation 1, UGBW must be approximated from Figure 58.
Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 k
50 k
VDD – /GND
VDD +
Rnull
CL
VI
+
Figure 60. Series-Resistance Circuit


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