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TLC320AC02C Datasheet(PDF) 52 Page - Texas Instruments |
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TLC320AC02C Datasheet(HTML) 52 Page - Texas Instruments |
52 / 86 page 4–5 Delay Is m Shift Clocks† Delay Is m Shift Clocks† Delay Is m Shift Clocks† Master FS Master FSD, Slave Device 1 FS Slave Device 1 FSD, Slave Device 2 FS Slave Device 2 FSD, Slave Device 3 FS Slave Device (n – 1) FSD, Slave Device n FS † The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word programs the master and all slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3, etc., have the same delay time. Figure 4 – 10. Master-Slave Frame-Sync Timing After a Delay Has Been Programmed Into the FSD Registers 1/2 Period Sampling Period FSD Value MP MP MP MP MP MP MS MS MP MP MP SP SP MP MP MP MS SP SP SP SS MS SS MS SS t = 0 t = 1 t = 2 Master AIC Only Primary Frame Sync FS Master AIC Only Primary and Secondary Frame Sync FS Master and Slave AIC Primary Frame Sync FS Master and Slave AIC Primary and Secondary Frame Sync FS MP = Master Primary MS = Master Secondary SP = Slave Primary SS = Slave Secondary SP Figure 4 – 11. Master and Slave Frame-Sync Sequence with One Slave |
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