Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06011 Rev. *A
Revised December 26, 2002
60A
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 9 FIFO (CY7C460A)
• 16K x 9 FIFO (CY7C462A)
• 32K x 9 FIFO (CY7C464A)
• 64K x 9 FIFO (CY7C466A)
• 10-ns access times, 20-ns read/write cycle times
• High-speed 50-MHz read/write independent of
depth/width
• Low operating power
—ICC= 60 mA
—ISB =8 mA
• Asynchronous read/write
• Empty and Full flags
• Half Full flag (in standalone mode)
• Retransmit (in standalone mode)
• TTL-compatible
• Width and Depth Expansion Capability
• 5V
± 10% supply
• PLCC, LCC, 300-mil and 600-mil DIP packaging
• Three-state outputs
• Pin compatible density upgrade to CY7C42X/46X family
• Pin compatible and functionally equivalent to IDT7205,
IDT7206, IDT7207, IDT7208
Functional Description
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in
first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it
was written. Full and Empty flags are provided to prevent over-
run and underrun. Three additional pins are also provided to
facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one
device to another by passing tokens.
The read and write operations may be asynchronous; each
can occur at a rate of up to 50 MHz. The write operation occurs
when the Write (W) signal is LOW. Read occurs when Read
(R) goes LOW. The nine data outputs go to the high-imped-
ance state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the stan-
dalone (single device) and width expansion configurations. In
the depth expansion configuration, this pin provides the ex-
pansion out (XO) information that is used to tell the next FIFO
that it will be activated.
In the standalone and width expansion configurations, a LOW
on the Retransmit (RT) input causes the FIFOs to retransmit
the data. Read Enable (R) and Write Enable (W) must both be
HIGH during a retransmit cycle, and then R is used to access
the data.
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
fabricated using Cypress’s advanced 0.5µ RAM3 CMOS tech-
nology. Input ESD protection is greater than 2000V and
latch-up is prevented by careful layout and the use of guard
rings.
32K x
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
GND
VCC
D4
FL/RT
MR
EF
XO/HF
Q7
R
PLCC/LCC
Top View
Q3
Q8
D5
D6
D7
Q6
Q5
Q4
4
3
2
1
32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
FL/RT
MR
EF
XO/HF
Q7
D6
Q6
D7
NC
READ
CONTROL
WRITE
CONTROL
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
RAM ARRAY
8K x 9
16K x 9
9
DATAINPUTS
(D0−D 8)
THREE–
STATE
BUFFERS
DATA OUTPUTS
(Q0-Q 8)
W
READ
POINTER
FLAG
LOGIC
R
XI
EF
FF
XO/HF
MR
FL/RT
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
C46XA–1
C46XA–2
C46XA–3
7C460A
7C462A
7C464A
7C460A
7C462A
7C464A
64K x 9
7C466A
7C466A
DUAL PORT
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