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LP3923 Datasheet(PDF) 4 Page - Texas Instruments |
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LP3923 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 37 page LDO7 VIN2 LDO6 LDO5 LDO4 LDO3 TX_EN RX_EN TCXO_EN LDO2 LDO8 IMON RESET_N PS_HOLD VIN1 GND SDA PON_N SEL LDO1 BATT SCL PWR_ON HF_PWR SW CHG_IN ACOK_N FB GNDB VINB 5 4 3 2 1 A 5 4 3 2 1 B C D E F LP3923 SNVS567B – APRIL 2010 – REVISED MAY 2013 www.ti.com Device Pin Diagram Table 1. LP3923 PIN DESCRIPTIONS(1) Pin Number Name Type Description A1 LDO4 A LDO4 Output A2 LDO5 A LDO5 Output A3 LDO6 A LDO6 Output A4 VIN2 P Input for LDO3 -LDO8 A5 LDO7 A LDO7 Output B1 LDO2 A LDO2 Output B2 TCXO_EN DI Enable control input for LDO4. HIGH = Enable, LOW = Disable (SLEEP Mode). B3 RX_EN DI Enable control input for LDO5. HIGH = Enable, LOW = Disable. B4 TX_EN DI Enable control input for LDO6. HIGH = Enable, LOW = Disable. B5 LDO3 A LDO3 Output C1 VIN1 P Input for LDO1 and LDO2 C2 PS_HOLD DI Power Supply Hold Input C3 RESET_N DO Reset Output. Pin stays LOW during power up sequence Charging current monitor output. This pin presents an analog voltage C4 IMON A representation of the charging current. C5 LDO8 A LDO8 Output D1 LDO1 A LDO1 Output D2 SEL DI LDO1 and LDO2 default voltage selection. D3 PON_N DO State of PWR_ON inverted. Digital output referred to LDO3. D4 SDA DI/O Serial Interface, Data Input/Output Open Drain output, external pull up resistor is needed, typ. 1.5 k Ω. D5 GND G IC Ground pin E1 SW A Buck Output (1) A: Analog Pin D: Digital Pin I: Input Pin DI/O: Digital Input/Output Pin G: Ground O: Output Pin P: Power Connection 4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LP3923 |
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