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DSC1025DI2 Datasheet(PDF) 2 Page - Micrel Semiconductor |
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DSC1025DI2 Datasheet(HTML) 2 Page - Micrel Semiconductor |
2 / 7 page All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Micrel, Inc. Micrel Inc. may update or make changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not limited to implied warranties of merchantability or fitness for a particular use. Page 2 MK-Q-B-P-D-031809-04-7 DSC1025 2.5V Low-Power CMOS Oscillator Absolute Maximum Ratings1 Item Min. Max Unit Condition Input Voltage -0.3 VDD+0.3 V Junction Temp - +150 °C Storage Temp -55 +150 °C Soldering Temp - +260 °C 40 sec max. ESD HBM MM CDM - 2000 200 500 V Ordering Code Recommended Operating Conditions Specifications Notes: 1. Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated beyond these limits. 2. tSU is time to stable output frequency after VDD is applied. tSU and tEN (after EN is asserted) are identical values. 3. See typical cycle to cycle jitter graph for frequency dependence. Parameter Symbol Range Supply Voltage VDD 2.3 to 2.7V Output Load ZL R>10KΩ, C≤15pF Operating Temperature Option 1 Option 2 Option 3 T -40 − +85 °C -20 − +70 °C 0 − +70 °C Parameter Symbol Condition Min. Typ. Max. Unit Frequency f0 Single Frequency 1 150 MHz Frequency Tolerance Option 1 Option 2 Option 3 Δf -40°C to +85°C -20°C to +70°C 0°C to +70°C ±25,±50 ±25,±50 ±25,±50 ppm Supply Current, no load IDD CL=0p RL=∞ T=25° C 1 to 40MHz 40 to 80MHz 80 to 125MHz 125 to 150MHz 3 4 5 6 10 mA Supply Current, standby IDD T=25°C 1.0 uA Output Logic Levels Output logic high Output logic low VOH VOL CL=15pF 0.8*VDD - - 0.2*VDD Volts Output Transition time Rise Time Fall Time tR tF CL=15pF; T=25°C 20%/80%*VDD 1.3 1.3 2 2 ns Output Startup Time2 tSU T=25°C 1.5 3 ms Output Disable Time tDA 20 100 ns Output Duty Cycle SYM 45 55 % Input Logic Levels Input logic high Input logic low VIH VIL 0.75*VDD - - 0.25* VDD Volts Jitter, Cycle to Cycle JCC F = 100MHz3 95 ps DSC1025 032.0000 Family Output Freq 1.0 to 150MHz CE1 Package, Temp & Stability - T Tape/ Reel * See Ordering Information for details |
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