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TVP5146PFP Datasheet(PDF) 79 Page - Texas Instruments |
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TVP5146PFP Datasheet(HTML) 79 Page - Texas Instruments |
79 / 100 page 2−64 2.11.85 Interrupt Status 0 Register Subaddress F2h Read only 7 6 5 4 3 2 1 0 FIFO THRS TTX WSS VPS VITC CC F2 CC F1 Line FIFO THRS: FIFO threshold passed, masked 0 = Not passed 1 = Passed TTX: Teletext data available masked 0 = Not available 1 = Available WSS: WSS data available masked 0 = Not available 1 = Available VPS: VPS data available masked 0 = Not available 1 = Available VITC: VITC data available masked 0 = Not available 1 = Available CC F2: CC field 2 data available masked 0 = Not available 1 = Available CC F1: CC field 1 data available masked 0 = Not available 1 = Available Line: Line number interrupt masked 0 = Not available 1 = Available See also the interrupt status 1 register at subaddress F3h (see Section 2.11.86). The interrupt status 0 and 1 registers represent the interrupt status after applying mask bits. Therefore, the status bits are the result of a logical AND between the raw status and mask bits. The external interrupt pin is derived from this register as an OR function of all nonmasked interrupts in this register. Reading data from the corresponding register does not clear the status flags automatically. These flags are reset using the corresponding bits in interrupt clear 0 and 1 registers. |
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