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TL750M12-Q1 Datasheet(PDF) 3 Page - Texas Instruments

Part No. TL750M12-Q1
Description  AUTOMOTIVE LOW-DROPOUT VOLTAGE REGULATORS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TL750M12-Q1 Datasheet(HTML) 3 Page - Texas Instruments

 
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TL750Mxx-Q1, TL751Mxx-Q1
www.ti.com
SGLS312J
– SEPTEMBER 2005 – REVISED JUNE 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Continuous input voltage
26 V
Transient input voltage (see Figure 4)
60 V
Continuous reverse input voltage
–15 V
Transient reverse input voltage
t = 100 ms
–50 V
KTT package (3 pin)
26.9
°C/W
θJA
Package thermal impedance(2) (3)
KTT package (5 pin)
26.5
°C/W
KVU package
38.6
°C/W
TJ
Virtual junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. Due to variation in
individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power
levels slightly above or below the rated dissipation.
(3)
The package thermal impedance is calculated in accordance with JESD 51.
THERMAL INFORMATION
TL750M05
THERMAL METRIC(1)
KTT
UNITS
3 PINS
θJA
Junction-to-ambient thermal resistance(2)
27.5
θJCtop
Junction-to-case (top) thermal resistance(3)
43.2
θJB
Junction-to-board thermal resistance(4)
17.3
°C/W
ψJT
Junction-to-top characterization parameter(5)
2.8
ψJB
Junction-to-board characterization parameter(6)
9.3
θJCbot
Junction-to-case (bottom) thermal resistance(7)
0.3
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
TL75xM05
6
26
VI
Input voltage
TL75xM08
9
26
V
TL75xM12
13
26
VIH
High-level ENABLE input voltage
TL751Mxx
2
15
V
VIL
Low-level ENABLE input voltage
TL751Mxx
0
0.8
V
IO
Output current
TL75xMxx
750
mA
TJ
Operating virtual junction temperature
TL75xMxx
–40
125
°C
Copyright
© 2005–2011, Texas Instruments Incorporated
3


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