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TL3842BDR-8 Datasheet(PDF) 13 Page - Texas Instruments |
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TL3842BDR-8 Datasheet(HTML) 13 Page - Texas Instruments |
13 / 24 page www.ti.com Shutdown Technique 330 Ω 1 k Ω 500 Ω To Current-Sense Resistor Shutdown Shutdown COMP VREF ISENSE RT 0.1 µF CT R1 R2 ISENSE RSENSE C VREF RT/CT ISENSE TL284xB, TL384xB HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS SLVS610B – AUGUST 2006 – REVISED JULY 2007 APPLICATION INFORMATION (continued) The PWM controller (see Figure 5) can be shut down by two methods: either raise the voltage at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset. Figure 5. Shutdown Techniques A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 6). Note that capacitor C forms a filter with R2 to suppress the leading-edge switch spikes. Figure 6. Slope Compensation 13 Submit Documentation Feedback |
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